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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dc_fsm.v] - Diff between revs 10 and 141

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Line 41... Line 41...
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: or1200_dc_fsm.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Minor update: 
 
// Bugs fixed. 
 
//
 
// Revision 1.9  2004/06/08 18:17:36  lampret
 
// Non-functional changes. Coding style fixes.
 
//
// Revision 1.8  2004/04/05 08:29:57  lampret
// Revision 1.8  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
// Merged branch_qmem into main tree.
//
//
// Revision 1.7.4.1  2003/07/08 15:36:37  lampret
// Revision 1.7.4.1  2003/07/08 15:36:37  lampret
// Added embedded memory QMEM.
// Added embedded memory QMEM.
Line 115... Line 122...
        clk, rst,
        clk, rst,
 
 
        // Internal i/f to top level DC
        // Internal i/f to top level DC
        dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
        dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
        tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
        tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
        dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
        dcram_we, biu_read, biu_write, biu_sel, first_hit_ack, first_miss_ack, first_miss_err,
        burst, tag_we, dc_addr
        burst, tag_we, tag_valid, dc_addr
);
);
 
 
//
//
// I/O
// I/O
//
//
Line 137... Line 144...
input   [31:0]                   start_addr;
input   [31:0]                   start_addr;
output  [31:0]                   saved_addr;
output  [31:0]                   saved_addr;
output  [3:0]                    dcram_we;
output  [3:0]                    dcram_we;
output                          biu_read;
output                          biu_read;
output                          biu_write;
output                          biu_write;
 
output              biu_sel;
output                          first_hit_ack;
output                          first_hit_ack;
output                          first_miss_ack;
output                          first_miss_ack;
output                          first_miss_err;
output                          first_miss_err;
output                          burst;
output                          burst;
output                          tag_we;
output                          tag_we;
 
output              tag_valid;
output  [31:0]                   dc_addr;
output  [31:0]                   dc_addr;
 
 
//
//
// Internal wires and regs
// Internal wires and regs
//
//
Line 154... Line 163...
reg     [2:0]                    cnt;
reg     [2:0]                    cnt;
reg                             hitmiss_eval;
reg                             hitmiss_eval;
reg                             store;
reg                             store;
reg                             load;
reg                             load;
reg                             cache_inhibit;
reg                             cache_inhibit;
 
reg             cache_miss;
 
//wire                          tagcomp_miss_wide;
wire                            first_store_hit_ack;
wire                            first_store_hit_ack;
 
 
//
//
// Generate of DCRAM write enables
// Generate of DCRAM write enables
//
//
assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcqmem_sel_i;
//assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcqmem_sel_i;
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
assign dcram_we = {4{load & biudata_valid & !cache_inhibit & !hitmiss_eval}} |
 
                  {4{first_store_hit_ack}} & dcqmem_sel_i;
 
//assign tag_we = biu_read & biudata_valid & !cache_inhibit;
 
assign tag_we = load & (biudata_valid & (!cache_inhibit | !cache_miss) | biudata_error) & !hitmiss_eval |
 
                store & (biudata_valid & cache_inhibit & !cache_miss | biudata_error) & !hitmiss_eval;
 
assign tag_valid = biudata_valid & !cache_inhibit;
 
 
//
//
// BIU read and write
// BIU read and write
//
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
//assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
assign biu_write = store;
//assign biu_read = ((hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load)) & (dcqmem_cycstb_i | biudata_valid);
 
assign biu_read = (state == `OR1200_DCFSM_CLOAD) & (hitmiss_eval ? ((tagcomp_miss | dcqmem_ci_i) & dcqmem_cycstb_i) : (cache_miss & !cache_inhibit & biudata_valid | dcqmem_cycstb_i & !biudata_error)) |
 
                  (state == `OR1200_DCFSM_LREFILL3) & !(biudata_valid & !cnt) & !biudata_error;
 
//assign biu_write = store;
 
//assign biu_write = store & dcqmem_cycstb_i;
 
assign biu_write = store & dcqmem_cycstb_i;
 
assign biu_sel = load;
 
 
assign dc_addr = (biu_read | biu_write) & !hitmiss_eval ? saved_addr : start_addr;
//assign dc_addr = (biu_read | biu_write) & !hitmiss_eval ? saved_addr : start_addr;
 
assign dc_addr = (!(load | store) | hitmiss_eval) ? start_addr : saved_addr;
assign saved_addr = saved_addr_r;
assign saved_addr = saved_addr_r;
 
 
//
//
// Assert for cache hit first word ready
// Assert for cache hit first word ready
// Assert for store cache hit first word ready
// Assert for store cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
// Assert for cache miss first word stored/loaded with an error
//
//
assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcqmem_ci_i | first_store_hit_ack;
//assign tagcomp_miss_wide = tagcomp_miss | (saved_addr != start_addr);
assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcqmem_ci_i;
//assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss_wide & !cache_inhibit | first_store_hit_ack;
 
assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i | first_store_hit_ack;
 
//assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss_wide & biudata_valid & !cache_inhibit;
 
assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !hitmiss_eval & !cache_miss & biudata_valid & !cache_inhibit;
assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
 
 
//
//
// Assert burst when doing reload of complete cache line
// Assert burst when doing reload of complete cache line
//
//
assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
//assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
                | (state == `OR1200_DCFSM_LREFILL3)
//              | (state == `OR1200_DCFSM_LREFILL3)
`ifdef OR1200_DC_STORE_REFILL
//`ifdef OR1200_DC_STORE_REFILL
                | (state == `OR1200_DCFSM_SREFILL4)
//              | (state == `OR1200_DCFSM_SREFILL4)
`endif
//`endif
                ;
//              ;
 
assign burst = load & (hitmiss_eval ? !dcqmem_ci_i : !cache_inhibit);
 
 
//
//
// Main DC FSM
// Main DC FSM
//
//
always @(posedge clk or posedge rst) begin
always @(posedge clk or posedge rst) begin
Line 203... Line 230...
                saved_addr_r <= #1 32'b0;
                saved_addr_r <= #1 32'b0;
                hitmiss_eval <= #1 1'b0;
                hitmiss_eval <= #1 1'b0;
                store <= #1 1'b0;
                store <= #1 1'b0;
                load <= #1 1'b0;
                load <= #1 1'b0;
                cnt <= #1 3'b000;
                cnt <= #1 3'b000;
 
        cache_miss <= #1 1'b0;
                cache_inhibit <= #1 1'b0;
                cache_inhibit <= #1 1'b0;
        end
        end
        else
        else
        case (state)    // synopsys parallel_case
        case (state)    // synopsys parallel_case
                `OR1200_DCFSM_IDLE :
        `OR1200_DCFSM_IDLE : begin
                        if (dc_en & dcqmem_cycstb_i & dcqmem_we_i) begin        // store
            if (dcqmem_we_i & dc_en & dcqmem_cycstb_i) // store
                                state <= #1 `OR1200_DCFSM_CSTORE;
                                state <= #1 `OR1200_DCFSM_CSTORE;
                                saved_addr_r <= #1 start_addr;
            else if (!dcqmem_we_i & dc_en & dcqmem_cycstb_i) // store
                                hitmiss_eval <= #1 1'b1;
 
                                store <= #1 1'b1;
 
                                load <= #1 1'b0;
 
                                cache_inhibit <= #1 1'b0;
 
                        end
 
                        else if (dc_en & dcqmem_cycstb_i) begin         // load
 
                                state <= #1 `OR1200_DCFSM_CLOAD;
                                state <= #1 `OR1200_DCFSM_CLOAD;
                                saved_addr_r <= #1 start_addr;
            cache_inhibit <= #1 1'b0;         // not dcqmem_ci_i because it is delayed (due to DTLB)
                                hitmiss_eval <= #1 1'b1;
            hitmiss_eval <= #1 dc_en & dcqmem_cycstb_i  ;
                                store <= #1 1'b0;
            store <= #1 dc_en & dcqmem_cycstb_i & dcqmem_we_i;
                                load <= #1 1'b1;
            load <= #1 dc_en & dcqmem_cycstb_i & !dcqmem_we_i;
                                cache_inhibit <= #1 1'b0;
 
                        end
 
                        else begin                                                      // idle
 
                                hitmiss_eval <= #1 1'b0;
 
                                store <= #1 1'b0;
 
                                load <= #1 1'b0;
 
                                cache_inhibit <= #1 1'b0;
 
                        end
                        end
                `OR1200_DCFSM_CLOAD: begin              // load
                `OR1200_DCFSM_CLOAD: begin              // load
                        if (dcqmem_cycstb_i & dcqmem_ci_i)
            if (!hitmiss_eval && cache_miss && !cache_inhibit && biudata_valid) begin
                                cache_inhibit <= #1 1'b1;
 
                        if (hitmiss_eval)
 
                                saved_addr_r[31:13] <= #1 start_addr[31:13];
 
                        if ((hitmiss_eval & !dcqmem_cycstb_i) ||                                        // load aborted (usually caused by DMMU)
 
                            (biudata_error) ||                                                                          // load terminated with an error
 
                            ((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin      // load from cache-inhibited area
 
                                state <= #1 `OR1200_DCFSM_IDLE;
 
                                hitmiss_eval <= #1 1'b0;
 
                                load <= #1 1'b0;
 
                                cache_inhibit <= #1 1'b0;
 
                        end
 
                        else if (tagcomp_miss & biudata_valid) begin    // load missed, finish current external load and refill
 
                                state <= #1 `OR1200_DCFSM_LREFILL3;
                                state <= #1 `OR1200_DCFSM_LREFILL3;
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
 
                                hitmiss_eval <= #1 1'b0;
 
                                cnt <= #1 `OR1200_DCLS-2;
 
                                cache_inhibit <= #1 1'b0;
 
                        end
                        end
                        else if (!tagcomp_miss & !dcqmem_ci_i) begin    // load hit, finish immediately
            else if (!dcqmem_cycstb_i || !hitmiss_eval && (biudata_valid || biudata_error) || hitmiss_eval && !tagcomp_miss && !dcqmem_ci_i) begin
                                state <= #1 `OR1200_DCFSM_IDLE;
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
 
                                load <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
 
                        end
                        end
                        else                                            // load in-progress
 
                                hitmiss_eval <= #1 1'b0;
                                hitmiss_eval <= #1 1'b0;
 
            cnt <= #1 `OR1200_DCLS-2;
 
            if (hitmiss_eval) begin
 
                cache_inhibit <= #1 dcqmem_ci_i;
 
                cache_miss <= #1 tagcomp_miss;
                end
                end
                `OR1200_DCFSM_LREFILL3 : begin
            if (hitmiss_eval)
                        if (biudata_valid && (|cnt)) begin              // refill ack, more loads to come
                saved_addr_r <= #1 start_addr;
                                cnt <= #1 cnt - 3'd1;
            else if (biudata_valid)
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'b1;
                        end
                        end
                        else if (biudata_valid) begin                   // last load of line refill
        `OR1200_DCFSM_LREFILL3 : begin
 
            if (!dc_en || biudata_valid && !cnt || biudata_error) begin                     // finish/abort
                                state <= #1 `OR1200_DCFSM_IDLE;
                                state <= #1 `OR1200_DCFSM_IDLE;
                                load <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                        end
 
            if (biudata_valid) begin
 
                cnt <= #1 cnt - 1'b1;
 
                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'b1;
 
            end
                end
                end
                `OR1200_DCFSM_CSTORE: begin             // store
                `OR1200_DCFSM_CSTORE: begin             // store
                        if (dcqmem_cycstb_i & dcqmem_ci_i)
            hitmiss_eval <= 1'b0;
                                cache_inhibit <= #1 1'b1;
            if (hitmiss_eval) begin
                        if (hitmiss_eval)
                cache_inhibit <= #1 dcqmem_ci_i;
                                saved_addr_r[31:13] <= #1 start_addr[31:13];
                cache_miss <= #1 tagcomp_miss;
                        if ((hitmiss_eval & !dcqmem_cycstb_i) ||        // store aborted (usually caused by DMMU)
 
                            (biudata_error) ||                                          // store terminated with an error
 
                            ((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin      // store to cache-inhibited area
 
                                state <= #1 `OR1200_DCFSM_IDLE;
 
                                hitmiss_eval <= #1 1'b0;
 
                                store <= #1 1'b0;
 
                                cache_inhibit <= #1 1'b0;
 
                        end
                        end
 
            if (hitmiss_eval)
 
                saved_addr_r <= #1 start_addr;
`ifdef OR1200_DC_STORE_REFILL
`ifdef OR1200_DC_STORE_REFILL
                        else if (tagcomp_miss & biudata_valid) begin    // store missed, finish write-through and doq load refill
            else if (biudata_valid)
 
                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'b1;
 
            cnt <= #1 `OR1200_DCLS-1;
 
            if (!hitmiss_eval && cache_miss && !cache_inhibit && biudata_valid) begin
                                state <= #1 `OR1200_DCFSM_SREFILL4;
                                state <= #1 `OR1200_DCFSM_SREFILL4;
                                hitmiss_eval <= #1 1'b0;
 
                                store <= #1 1'b0;
                                store <= #1 1'b0;
                                load <= #1 1'b1;
                                load <= #1 1'b1;
                                cnt <= #1 `OR1200_DCLS-1;
 
                                cache_inhibit <= #1 1'b0;
 
                        end
                        end
 
            else
`endif
`endif
                        else if (biudata_valid) begin                   // store hit, finish write-through
            if (!dcqmem_cycstb_i || !hitmiss_eval && (biudata_error || biudata_valid)) begin
                                state <= #1 `OR1200_DCFSM_IDLE;
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
 
                                store <= #1 1'b0;
                                store <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
 
                        end
 
                        else                                            // store write-through in-progress
 
                                hitmiss_eval <= #1 1'b0;
 
                        end
                        end
`ifdef OR1200_DC_STORE_REFILL
`ifdef OR1200_DC_STORE_REFILL
                `OR1200_DCFSM_SREFILL4 : begin
                `OR1200_DCFSM_SREFILL4 : begin
                        if (biudata_valid && (|cnt)) begin              // refill ack, more loads to come
            if (!dc_en) begin                       // somebody just turned off DC therefore we abort
 
                cnt <= #1 3'd0;                     // DC will have to be invalidated before
 
                state <= #1 `OR1200_DCFSM_IDLE;     // it can be turned on again
 
                load <= #1 1'b0;
 
            end
 
            else if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
                                cnt <= #1 cnt - 1'd1;
                                cnt <= #1 cnt - 1'd1;
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
                        end
                        end
                        else if (biudata_valid) begin                   // last load of line refill
                        else if (biudata_valid) begin                   // last load of line refill
                                state <= #1 `OR1200_DCFSM_IDLE;
                                state <= #1 `OR1200_DCFSM_IDLE;
                                load <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                        end
                end
 
`endif
`endif
 
        end
 
 
                default:
                default:
                        state <= #1 `OR1200_DCFSM_IDLE;
                        state <= #1 `OR1200_DCFSM_IDLE;
        endcase
        endcase
end
end
 
 

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