| Line 123... |
Line 123... |
//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [31:0] addr_r;
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reg [31:0] addr_r;
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reg [2:0] state;
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reg [2:0] state;
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reg [2:0] cnt;
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reg [`OR1200_DCLS-1:0] cnt;
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reg hitmiss_eval;
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reg hitmiss_eval;
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reg store;
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reg store;
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reg load;
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reg load;
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reg cache_inhibit;
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reg cache_inhibit;
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reg cache_miss;
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reg cache_miss;
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| Line 148... |
Line 148... |
wire dcram_we_during_line_load;
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wire dcram_we_during_line_load;
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wire tagram_we_end_of_loadstore_loop;
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wire tagram_we_end_of_loadstore_loop;
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wire tagram_dirty_bit_set;
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wire tagram_dirty_bit_set;
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wire writethrough;
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wire writethrough;
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wire cache_inhibit_with_eval;
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wire cache_inhibit_with_eval;
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wire [1:0] next_addr_word;
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wire [(`OR1200_DCLS-1)-2:0] next_addr_word;
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//
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//
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// Cache inhibit
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// Cache inhibit
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//
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//
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| Line 266... |
Line 266... |
assign dcram_di_sel = load;
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assign dcram_di_sel = load;
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// Data to external bus - always from IU except in case of bursting back
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// Data to external bus - always from IU except in case of bursting back
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// the line to memory. (1 selects DCRAM)
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// the line to memory. (1 selects DCRAM)
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assign biu_do_sel = (state == `OR1200_DCFSM_LOOP2) & store;
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assign biu_do_sel = (state == `OR1200_DCFSM_LOOP2) & store;
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// 2-bit wire for calculating next word of burst write
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// 3-bit wire for calculating next word of burst write, depending on
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assign next_addr_word = addr_r[3:2] + 1;
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// line size of data cache.
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assign next_addr_word = addr_r[`OR1200_DCLS-1:2] + 1;
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// Address to cache RAM (tag address also derived from this)
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// Address to cache RAM (tag address also derived from this)
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assign dc_addr =
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assign dc_addr =
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// First check if we've got a block flush or WB op
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// First check if we've got a block flush or WB op
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((dc_block_flush & !cache_spr_block_flush) |
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((dc_block_flush & !cache_spr_block_flush) |
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| Line 283... |
Line 284... |
// Next, if in writeback loop, when ACKed must immediately
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// Next, if in writeback loop, when ACKed must immediately
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// output next word address (the RAM address takes a cycle
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// output next word address (the RAM address takes a cycle
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// to increment, but it's needed immediately for burst)
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// to increment, but it's needed immediately for burst)
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// otherwise, output our registered address.
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// otherwise, output our registered address.
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(state==`OR1200_DCFSM_LOOP2 & biudata_valid & store ) ?
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(state==`OR1200_DCFSM_LOOP2 & biudata_valid & store ) ?
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{addr_r[31:4], next_addr_word, 2'b00} : addr_r;
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{addr_r[31:`OR1200_DCLS], next_addr_word, 2'b00} : addr_r;
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`ifdef OR1200_DC_WRITETHROUGH
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`ifdef OR1200_DC_WRITETHROUGH
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`ifdef OR1200_DC_NOSTACKWRITETHROUGH
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`ifdef OR1200_DC_NOSTACKWRITETHROUGH
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assign writethrough = !dc_no_writethrough;
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assign writethrough = !dc_no_writethrough;
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`else
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`else
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| Line 340... |
Line 341... |
// Get the _early_ ack on first ACK back from wishbone during load only
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// Get the _early_ ack on first ACK back from wishbone during load only
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// Condition is that we're in the loop - that it's the first ack we get (can
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// Condition is that we're in the loop - that it's the first ack we get (can
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// tell from value of cnt), and we're loading a line to read from it (not
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// tell from value of cnt), and we're loading a line to read from it (not
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// loading to write to it, in the case of a write without writethrough.)
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// loading to write to it, in the case of a write without writethrough.)
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assign load_miss_ack = ((state== `OR1200_DCFSM_LOOP2) & load &
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assign load_miss_ack = ((state== `OR1200_DCFSM_LOOP2) & load &
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(cnt==`OR1200_DCLS-1) & biudata_valid &
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(cnt==((1 << `OR1200_DCLS) - 4)) & biudata_valid &
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!(dcqmem_we_i & !writethrough));
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!(dcqmem_we_i & !writethrough));
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assign load_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
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assign load_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
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load & cache_inhibit & biudata_valid;
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load & cache_inhibit & biudata_valid;
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| Line 360... |
Line 361... |
// Main DC FSM
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// Main DC FSM
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//
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//
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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if (rst == `OR1200_RST_VALUE) begin
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if (rst == `OR1200_RST_VALUE) begin
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state <= `OR1200_DCFSM_IDLE;
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state <= `OR1200_DCFSM_IDLE;
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addr_r <= 32'b0;
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addr_r <= 32'd0;
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hitmiss_eval <= 1'b0;
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hitmiss_eval <= 1'b0;
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store <= 1'b0;
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store <= 1'b0;
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load <= 1'b0;
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load <= 1'b0;
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cnt <= 3'd0;
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cnt <= `OR1200_DCLS'd0;
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cache_miss <= 1'b0;
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cache_miss <= 1'b0;
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cache_dirty_needs_writeback <= 1'b0;
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cache_dirty_needs_writeback <= 1'b0;
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cache_inhibit <= 1'b0;
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cache_inhibit <= 1'b0;
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did_early_load_ack <= 1'b0;
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did_early_load_ack <= 1'b0;
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cache_spr_block_flush <= 1'b0;
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cache_spr_block_flush <= 1'b0;
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| Line 428... |
Line 429... |
load <= 1'b1;
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load <= 1'b1;
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store <= 1'b0;
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store <= 1'b0;
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end // else: !if(dirty)
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end // else: !if(dirty)
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state <= `OR1200_DCFSM_LOOP2;
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state <= `OR1200_DCFSM_LOOP2;
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// Set the counter for the burst accesses
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// Set the counter for the burst accesses
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cnt <= `OR1200_DCLS-1;
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cnt <= ((1 << `OR1200_DCLS) - 4);
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end
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end
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else if (// Strobe goes low
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else if (// Strobe goes low
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!dcqmem_cycstb_i |
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!dcqmem_cycstb_i |
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// Cycle finishes
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// Cycle finishes
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(!hitmiss_eval & (biudata_valid | biudata_error)) |
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(!hitmiss_eval & (biudata_valid | biudata_error)) |
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| Line 451... |
Line 452... |
`OR1200_DCFSM_LOOP2 : begin // loop/abort
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`OR1200_DCFSM_LOOP2 : begin // loop/abort
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if (!dc_en| biudata_error) begin
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if (!dc_en| biudata_error) begin
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state <= `OR1200_DCFSM_IDLE;
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state <= `OR1200_DCFSM_IDLE;
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load <= 1'b0;
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load <= 1'b0;
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store <= 1'b0;
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store <= 1'b0;
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cnt <= 3'd0;
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cnt <= `OR1200_DCLS'd0;
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end
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end
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if (biudata_valid & (|cnt)) begin
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if (biudata_valid & (|cnt)) begin
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cnt <= cnt - 3'd1;
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cnt <= cnt - 4;
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addr_r[3:2] <= addr_r[3:2] + 1'b1;
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addr_r[`OR1200_DCLS-1:2] <= addr_r[`OR1200_DCLS-1:2] + 1;
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end
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end
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else if (biudata_valid & !(|cnt)) begin
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else if (biudata_valid & !(|cnt)) begin
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state <= `OR1200_DCFSM_LOOP3;
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state <= `OR1200_DCFSM_LOOP3;
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addr_r <= lsu_addr;
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addr_r <= lsu_addr;
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load <= 1'b0;
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load <= 1'b0;
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| Line 476... |
Line 477... |
`OR1200_DCFSM_LOOP3: begin // figure out next step
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`OR1200_DCFSM_LOOP3: begin // figure out next step
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if (cache_dirty_needs_writeback) begin
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if (cache_dirty_needs_writeback) begin
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// Just did store of the dirty line so now load new one
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// Just did store of the dirty line so now load new one
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load <= 1'b1;
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load <= 1'b1;
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// Set the counter for the burst accesses
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// Set the counter for the burst accesses
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cnt <= `OR1200_DCLS-1;
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cnt <= ((1 << `OR1200_DCLS) - 4);
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// Address of line to be loaded
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// Address of line to be loaded
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addr_r <= lsu_addr;
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addr_r <= lsu_addr;
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cache_dirty_needs_writeback <= 1'b0;
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cache_dirty_needs_writeback <= 1'b0;
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state <= `OR1200_DCFSM_LOOP2;
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state <= `OR1200_DCFSM_LOOP2;
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end // if (cache_dirty_needs_writeback)
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end // if (cache_dirty_needs_writeback)
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| Line 524... |
Line 525... |
`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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$display("%t: block flush: dirty block", $time);
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$display("%t: block flush: dirty block", $time);
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`endif
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`endif
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state <= `OR1200_DCFSM_LOOP2;
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state <= `OR1200_DCFSM_LOOP2;
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// Set the counter for the burst accesses
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// Set the counter for the burst accesses
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cnt <= `OR1200_DCLS-1;
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cnt <= ((1 << `OR1200_DCLS) - 4);
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end
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end
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else if (cache_spr_block_flush & !dirty)
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else if (cache_spr_block_flush & !dirty)
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begin
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begin
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// Line not dirty, just need to invalidate
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// Line not dirty, just need to invalidate
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state <= `OR1200_DCFSM_INV6;
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state <= `OR1200_DCFSM_INV6;
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