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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dc_ram.v] - Diff between revs 258 and 481

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Rev 258	Rev 481
Line 102...	Line 102...
`else	`else

`//`	`//`
`// Instantiation of RAM block`	`// Instantiation of RAM block`
`//`	`//`
`ifdef OR1200_DC_1W_4KB
`or1200_spram_32_bw #`	`or1200_spram_32_bw #`
`(`	`(`
`.aw(10),`	.aw(`OR1200_DCINDX),
`.dw(32)`	`.dw(dw)`
`)`	`)`
`endif
`ifdef OR1200_DC_1W_8KB
`or1200_spram_32_bw #`
`(`
`.aw(11),`
`.dw(32)`
`)`
`endif
`dc_ram`	`dc_ram`
`(`	`(`
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`.mbist_si_i(mbist_si_i),`	`.mbist_si_i(mbist_si_i),`

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