OpenCores

Rev 141	Rev 258
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`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// OR1200's DC TAG RAMs ////`	`//// OR1200's DC TAG RAMs ////`
`//// ////`	`//// ////`
`//// This file is part of the OpenRISC 1200 project ////`	`//// This file is part of the OpenRISC 1200 project ////`
`//// http://www.opencores.org/cores/or1k/ ////`	`//// http://opencores.org/project,or1k ////`
`//// ////`	`//// ////`
`//// Description ////`	`//// Description ////`
`//// Instatiation of data cache tag rams. ////`	`//// Instatiation of data cache tag rams. ////`
`//// ////`	`//// ////`
`//// To Do: ////`	`//// To Do: ////`
Line 39...	Line 39...
`//// Public License along with this source; if not, download it ////`	`//// Public License along with this source; if not, download it ////`
`//// from http://www.opencores.org/lgpl.shtml ////`	`//// from http://www.opencores.org/lgpl.shtml ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`
`//`
`// $Log: or1200_dc_tag.v,v $`	`// $Log: or1200_dc_tag.v,v $`
`// Revision 2.0 2010/06/30 11:00:00 ORSoC`	`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
`// Minor update:`	`// Minor update:`
`// Coding style changed.`	`// Coding style changed.`
`//`	`//`
`// Revision 1.5 2004/06/08 18:17:36 lampret`
`// Non-functional changes. Coding style fixes.`
`//`
`// Revision 1.4 2004/04/05 08:29:57 lampret`
`// Merged branch_qmem into main tree.`
`//`
`// Revision 1.2.4.1 2003/12/09 11:46:48 simons`
`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
`//`
`// Revision 1.2 2002/10/17 20:04:40 lampret`
`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
`//`
`// Revision 1.1 2002/01/03 08:16:15 lampret`
`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
`//`
`// Revision 1.8 2001/10/21 17:57:16 lampret`
`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
`//`
`// Revision 1.7 2001/10/14 13:12:09 lampret`
`// MP3 version.`
`//`
`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
`// no message`
`//`
`// Revision 1.2 2001/08/09 13:39:33 lampret`
`// Major clean-up.`
`//`
`// Revision 1.1 2001/07/20 00:46:03 lampret`
`// Development version of RTL. Libraries are missing.`
`//`
`//`

`// synopsys translate_off`	`// synopsys translate_off`
`include "timescale.v"	`include "timescale.v"
`// synopsys translate_on`	`// synopsys translate_on`
`include "or1200_defines.v"	`include "or1200_defines.v"
Line 93...	Line 60...
`// RAM BIST`	`// RAM BIST`
`mbist_si_i, mbist_so_o, mbist_ctrl_i,`	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
`endif	`endif

`// Internal i/f`	`// Internal i/f`
`addr, en, we, datain, tag_v, tag`	`addr, en, we, datain, tag_v, tag, dirty`
`);`	`);`

parameter dw = `OR1200_DCTAG_W;	parameter dw = `OR1200_DCTAG_W+1;
parameter aw = `OR1200_DCTAG;	parameter aw = `OR1200_DCTAG;

`//`	`//`
`// I/O`	`// I/O`
`//`	`//`
Line 109...	Line 76...
`input [aw-1:0] addr;`	`input [aw-1:0] addr;`
`input en;`	`input en;`
`input we;`	`input we;`
`input [dw-1:0] datain;`	`input [dw-1:0] datain;`
`output tag_v;`	`output tag_v;`
`output [dw-2:0] tag;`	`output [dw-3:0] tag;`
	`output dirty;`


`ifdef OR1200_BIST	`ifdef OR1200_BIST
`//`	`//`
`// RAM BIST`	`// RAM BIST`
`//`	`//`
Line 140...	Line 109...
`//`	`//`
`ifdef OR1200_DC_1W_4KB	`ifdef OR1200_DC_1W_4KB
`or1200_spram #`	`or1200_spram #`
`(`	`(`
`.aw(8),`	`.aw(8),`
`.dw(21)`	`.dw(21 + 1)`
`)`	`)`
`endif	`endif
`ifdef OR1200_DC_1W_8KB	`ifdef OR1200_DC_1W_8KB
`or1200_spram #`	`or1200_spram #`
`(`	`(`
`.aw(9),`	`.aw(9),`
`.dw(20)`	`.dw(20 + 1)`
`)`	`)`
`endif	`endif
`dc_tag0`	`dc_tag0`
`(`	`(`
`ifdef OR1200_BIST	`ifdef OR1200_BIST
Line 163...	Line 132...
`.clk(clk),`	`.clk(clk),`
`.ce(en),`	`.ce(en),`
`.we(we),`	`.we(we),`
`.addr(addr),`	`.addr(addr),`
`.di(datain),`	`.di(datain),`
`.doq({tag, tag_v})`	`.doq({tag, tag_v, dirty})`
`);`	`);`
`endif	`endif

`endmodule // or1200_dc_tag`	`endmodule // or1200_dc_tag`

`No newline at end of file`	`No newline at end of file`

Line 1...

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

////  OR1200's DC TAG RAMs                                        ////

////  OR1200's DC TAG RAMs                                        ////

////                                                              ////

////                                                              ////

////  This file is part of the OpenRISC 1200 project              ////

////  This file is part of the OpenRISC 1200 project              ////

////  http://www.opencores.org/cores/or1k/                        ////

////  http://opencores.org/project,or1k                           ////

////                                                              ////

////                                                              ////

////  Description                                                 ////

////  Description                                                 ////

////  Instatiation of data cache tag rams.                        ////

////  Instatiation of data cache tag rams.                        ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////  To Do:                                                      ////

Line 39...

//// Public License along with this source; if not, download it   ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

//

//

// CVS Revision History

//

// $Log: or1200_dc_tag.v,v $

// $Log: or1200_dc_tag.v,v $

// Revision 2.0  2010/06/30 11:00:00  ORSoC

// Revision 2.0  2010/06/30 11:00:00  ORSoC

// Minor update:

// Minor update:

// Coding style changed.

// Coding style changed.

//

//

// Revision 1.5  2004/06/08 18:17:36  lampret

// Non-functional changes. Coding style fixes.

//

// Revision 1.4  2004/04/05 08:29:57  lampret

// Merged branch_qmem into main tree.

//

// Revision 1.2.4.1  2003/12/09 11:46:48  simons

// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.

//

// Revision 1.2  2002/10/17 20:04:40  lampret

// Added BIST scan. Special VS RAMs need to be used to implement BIST.

//

// Revision 1.1  2002/01/03 08:16:15  lampret

// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.

//

// Revision 1.8  2001/10/21 17:57:16  lampret

// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.

//

// Revision 1.7  2001/10/14 13:12:09  lampret

// MP3 version.

//

// Revision 1.1.1.1  2001/10/06 10:18:36  igorm

// no message

//

// Revision 1.2  2001/08/09 13:39:33  lampret

// Major clean-up.

//

// Revision 1.1  2001/07/20 00:46:03  lampret

// Development version of RTL. Libraries are missing.

//

//

// synopsys translate_off

// synopsys translate_off

`include "timescale.v"

`include "timescale.v"

// synopsys translate_on

// synopsys translate_on

`include "or1200_defines.v"

`include "or1200_defines.v"

Line 93...

Line 60...

        // RAM BIST

        // RAM BIST

        mbist_si_i, mbist_so_o, mbist_ctrl_i,

        mbist_si_i, mbist_so_o, mbist_ctrl_i,

`endif

`endif

        // Internal i/f

        // Internal i/f

        addr, en, we, datain, tag_v, tag

        addr, en, we, datain, tag_v, tag, dirty

);

);

parameter dw = `OR1200_DCTAG_W;

parameter dw = `OR1200_DCTAG_W+1;

parameter aw = `OR1200_DCTAG;

parameter aw = `OR1200_DCTAG;

//

//

// I/O

// I/O

//

//

Line 109...

Line 76...

input   [aw-1:0]         addr;

input   [aw-1:0]         addr;

input                           en;

input                           en;

input                           we;

input                           we;

input   [dw-1:0]         datain;

input   [dw-1:0]         datain;

output                          tag_v;

output                          tag_v;

output  [dw-2:0]         tag;

output  [dw-3:0]         tag;

output                          dirty;

`ifdef OR1200_BIST

`ifdef OR1200_BIST

//

//

// RAM BIST

// RAM BIST

//

//

Line 140...

Line 109...

//

//

`ifdef OR1200_DC_1W_4KB

`ifdef OR1200_DC_1W_4KB

   or1200_spram #

   or1200_spram #

      .aw(8),

      .aw(8),

      .dw(21)

      .dw(21 + 1)

`endif

`endif

`ifdef OR1200_DC_1W_8KB

`ifdef OR1200_DC_1W_8KB

   or1200_spram #

   or1200_spram #

      .aw(9),

      .aw(9),

      .dw(20)

      .dw(20 + 1)

`endif

`endif

   dc_tag0

   dc_tag0

`ifdef OR1200_BIST

`ifdef OR1200_BIST

Line 163...

Line 132...

      .clk(clk),

      .clk(clk),

      .ce(en),

      .ce(en),

      .we(we),

      .we(we),

      .addr(addr),

      .addr(addr),

      .di(datain),

      .di(datain),

      .doq({tag, tag_v})

      .doq({tag, tag_v, dirty})

);

);

`endif

`endif

endmodule // or1200_dc_tag

endmodule // or1200_dc_tag

 No newline at end of file

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