| Line 1... |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Data Cache top level ////
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//// OR1200's Data Cache top level ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Instantiation of all DC blocks. ////
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//// Instantiation of all DC blocks. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - Test error during line read or write ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Julius Baxter, julius@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000, 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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| Line 39... |
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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//
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//
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// $Log: or1200_dc_top.v,v $
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// $Log: or1200_dc_top.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Minor update:
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// Bugs fixed.
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// Bugs fixed.
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//
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//
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// Revision 1.8 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.6.4.2 2003/12/09 11:46:48 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.6.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.6 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.5 2002/08/18 19:54:47 lampret
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// Added store buffer.
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//
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// Revision 1.4 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.9 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// no message
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//
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// Revision 1.4 2001/08/13 03:36:20 lampret
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.2 2001/07/22 03:31:53 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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| Line 109... |
Line 60... |
module or1200_dc_top(
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module or1200_dc_top(
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// Rst, clk and clock control
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// Rst, clk and clock control
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clk, rst,
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clk, rst,
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// External i/f
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// External i/f
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dcsb_dat_o, dcsb_adr_o, dcsb_cyc_o, dcsb_stb_o, dcsb_we_o, dcsb_sel_o, dcsb_cab_o,
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dcsb_dat_o, dcsb_adr_o, dcsb_cyc_o, dcsb_stb_o, dcsb_we_o, dcsb_sel_o,
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dcsb_dat_i, dcsb_ack_i, dcsb_err_i,
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dcsb_cab_o, dcsb_dat_i, dcsb_ack_i, dcsb_err_i,
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// Internal i/f
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// Internal i/f
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dc_en,
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dc_en,
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dcqmem_adr_i, dcqmem_cycstb_i, dcqmem_ci_i,
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dcqmem_adr_i, dcqmem_cycstb_i, dcqmem_ci_i,
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dcqmem_we_i, dcqmem_sel_i, dcqmem_tag_i, dcqmem_dat_i,
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dcqmem_we_i, dcqmem_sel_i, dcqmem_tag_i, dcqmem_dat_i,
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dcqmem_dat_o, dcqmem_ack_o, dcqmem_rty_o, dcqmem_err_o, dcqmem_tag_o,
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dcqmem_dat_o, dcqmem_ack_o, dcqmem_rty_o, dcqmem_err_o, dcqmem_tag_o,
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dc_no_writethrough,
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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`endif
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// SPRs
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// SPRs
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spr_cs, spr_write, spr_dat_i
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spr_cs, spr_write, spr_dat_i, spr_addr, mtspr_dc_done
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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//
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//
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// I/O
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// I/O
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//
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//
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| Line 170... |
Line 124... |
output dcqmem_ack_o;
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output dcqmem_ack_o;
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output dcqmem_rty_o;
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output dcqmem_rty_o;
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output dcqmem_err_o;
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output dcqmem_err_o;
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output [3:0] dcqmem_tag_o;
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output [3:0] dcqmem_tag_o;
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input dc_no_writethrough;
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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//
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//
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// RAM BIST
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// RAM BIST
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//
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//
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input mbist_si_i;
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input mbist_si_i;
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| Line 185... |
Line 141... |
// SPR access
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// SPR access
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//
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//
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input spr_cs;
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input spr_cs;
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input spr_write;
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input spr_write;
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input [31:0] spr_dat_i;
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input [31:0] spr_dat_i;
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input [aw-1:0] spr_addr;
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output mtspr_dc_done;
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`ifdef OR1200_NO_DC
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// Bypass cache
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// IF to external memory
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assign dcsb_dat_o = dcqmem_dat_i;
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assign dcsb_adr_o = dcqmem_adr_i;
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assign dcsb_cyc_o = dcqmem_cycstb_i;
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assign dcsb_stb_o = dcqmem_cycstb_i;
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assign dcsb_we_o = dcqmem_we_i;
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assign dcsb_sel_o = dcqmem_sel_i;
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assign dcsb_cab_o = 1'b0;
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// IF to internal memory
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assign dcqmem_dat_o = dcsb_dat_i;
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assign dcqmem_ack_o = dcsb_ack_i;
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assign dcqmem_err_o = dcsb_err_i;
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assign dcqmem_rty_o = ~dcqmem_ack_o;
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assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
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assign mtspr_dc_done = 1'b1;
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`else
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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wire tag_v;
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wire tag_v;
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wire [`OR1200_DCTAG_W-2:0] tag;
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wire [`OR1200_DCTAG_W-2:0] tag;
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wire dirty;
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wire [dw-1:0] to_dcram;
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wire [dw-1:0] to_dcram;
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wire [dw-1:0] from_dcram;
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wire [dw-1:0] from_dcram;
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wire [31:0] saved_addr;
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wire [3:0] dcram_we;
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wire [3:0] dcram_we;
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wire dctag_we;
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wire dctag_we;
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wire [31:0] dc_addr;
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wire [31:0] dc_addr;
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wire dcfsm_biu_read;
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wire dcfsm_biu_read;
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wire dcfsm_biu_write;
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wire dcfsm_biu_write;
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wire dcfsm_biu_sel;
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wire dcfsm_dcram_di_sel;
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wire dcfsm_biu_do_sel;
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reg tagcomp_miss;
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reg tagcomp_miss;
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wire [`OR1200_DCINDXH:`OR1200_DCLS] dctag_addr;
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wire [`OR1200_DCINDXH:`OR1200_DCLS] dctag_addr;
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wire dctag_en;
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wire dctag_en;
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wire dctag_v;
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wire dctag_v;
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wire dc_inv;
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wire dctag_dirty;
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wire dc_block_invalidate;
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wire dc_block_flush;
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wire dc_block_writeback;
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wire dcfsm_first_hit_ack;
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wire dcfsm_first_hit_ack;
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wire dcfsm_first_miss_ack;
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wire dcfsm_first_miss_ack;
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wire dcfsm_first_miss_err;
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wire dcfsm_first_miss_err;
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wire dcfsm_burst;
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wire dcfsm_burst;
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wire dcfsm_tag_we;
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wire dcfsm_tag_we;
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wire dcfsm_tag_valid;
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wire dcfsm_tag_valid;
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wire dcfsm_tag_dirty;
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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//
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//
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// RAM BIST
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// RAM BIST
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//
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//
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wire mbist_ram_so;
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wire mbist_ram_so;
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| Line 222... |
Line 211... |
wire mbist_ram_si = mbist_si_i;
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wire mbist_ram_si = mbist_si_i;
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wire mbist_tag_si = mbist_ram_so;
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wire mbist_tag_si = mbist_ram_so;
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assign mbist_so_o = mbist_tag_so;
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assign mbist_so_o = mbist_tag_so;
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`endif
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`endif
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// Address out to external bus - always from FSM
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assign dcsb_adr_o = dc_addr;
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//
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//
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// Simple assignments
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// SPR register decodes
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//
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//
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assign dcsb_adr_o = dc_addr;
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`ifdef OR1200_DC_WRITETHROUGH
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assign dc_inv = spr_cs & spr_write;
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assign dc_block_invalidate = spr_cs & spr_write &
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assign dctag_we = dcfsm_tag_we | dc_inv;
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((spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBIR) |
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assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
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(spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBFR));
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assign dctag_en = dc_inv | dc_en;
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assign dc_block_flush = 0;
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//assign dctag_v = ~dc_inv;
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assign dc_block_writeback = 0;
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assign dctag_v = dc_inv ? 1'b0 : dcfsm_tag_valid;
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`else
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assign dc_block_invalidate = spr_cs & spr_write &
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(spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBIR);
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assign dc_block_flush = spr_cs & spr_write &
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(spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBFR);
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assign dc_block_writeback = spr_cs & spr_write &
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(spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBWR);
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`endif // !`ifdef OR1200_DC_WRITETHROUGH
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assign dctag_we = dcfsm_tag_we | dc_block_invalidate;
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assign dctag_addr = dc_block_invalidate ?
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spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] :
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dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
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assign dctag_en = dc_block_invalidate | dc_en;
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|
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assign dctag_v = dc_block_invalidate ? 1'b0 : dcfsm_tag_valid;
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assign dctag_dirty = dc_block_invalidate ? 1'b0 : dcfsm_tag_dirty;
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//
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//
|
// Data to BIU is from DCRAM when DC is enabled or from LSU when
|
// Data to BIU is from DCRAM when bursting lines back into memory
|
// DC is disabled
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//
|
//
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assign dcsb_dat_o = dcqmem_dat_i;
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assign dcsb_dat_o = dcfsm_biu_do_sel ? from_dcram : dcqmem_dat_i;
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//
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//
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// Bypases of the DC when DC is disabled
|
// Bypases of the DC when DC is disabled
|
//
|
//
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assign dcsb_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
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assign dcsb_cyc_o = (dc_en) ?
|
assign dcsb_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
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dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
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assign dcsb_we_o = (dc_en) ? dcfsm_biu_write : dcqmem_we_i;
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//assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcqmem_ci_i) ? 4'b1111 : dcqmem_sel_i;
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assign dcsb_stb_o = (dc_en) ?
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assign dcsb_sel_o = (dc_en & dcfsm_burst) ? 4'b1111 : dcqmem_sel_i;
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dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
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//assign dcsb_cab_o = (dc_en) ? dcsb_cyc_o & dcfsm_burst : 1'b0;
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|
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assign dcsb_we_o = (dc_en) ?
|
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dcfsm_biu_write : dcqmem_we_i;
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|
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assign dcsb_sel_o = (dc_en & dcfsm_burst) ?
|
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4'b1111 : dcqmem_sel_i;
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|
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assign dcsb_cab_o = dc_en & dcfsm_burst & dcsb_cyc_o;
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assign dcsb_cab_o = dc_en & dcfsm_burst & dcsb_cyc_o;
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assign dcqmem_rty_o = ~dcqmem_ack_o;
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assign dcqmem_rty_o = ~dcqmem_ack_o;
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assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
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assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
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|
|
//
|
//
|
// DC/LSU normal and error termination
|
// DC/LSU normal and error termination
|
//
|
//
|
assign dcqmem_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcsb_ack_i;
|
assign dcqmem_ack_o = dc_en ?
|
assign dcqmem_err_o = dc_en ? dcfsm_first_miss_err : dcsb_err_i;
|
dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcsb_ack_i;
|
|
|
//
|
assign dcqmem_err_o = dc_en ? dcfsm_first_miss_err : dcsb_err_i;
|
// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
|
|
//
|
|
//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcqmem_adr_i;
|
|
|
|
//
|
//
|
// Select between input data generated by LSU or by BIU
|
// Select between input data generated by LSU or by BIU
|
//
|
//
|
//assign to_dcram = (dcfsm_biu_read) ? dcsb_dat_i : dcqmem_dat_i;
|
assign to_dcram = (dcfsm_dcram_di_sel) ? dcsb_dat_i : dcqmem_dat_i;
|
assign to_dcram = (dcfsm_biu_sel) ? dcsb_dat_i : dcqmem_dat_i;
|
|
|
|
//
|
//
|
// Select between data generated by DCRAM or passed by BIU
|
// Select between data generated by DCRAM or passed by BIU
|
//
|
//
|
assign dcqmem_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
|
assign dcqmem_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
|
|
//assign dcqmem_dat_o = !dc_en ? dcsb_dat_i : from_dcram;
|
|
|
//
|
//
|
// Tag comparison
|
// Tag comparison
|
//
|
//
|
//always @(tag or saved_addr or tag_v) begin
|
wire [31:`OR1200_DCTAGL] dcqmem_adr_i_tag;
|
// if ((tag != saved_addr[31:`OR1200_DCTAGL]) || !tag_v)
|
assign dcqmem_adr_i_tag = dcqmem_adr_i[31:`OR1200_DCTAGL];
|
|
|
always @(tag or dcqmem_adr_i or tag_v) begin
|
always @(tag or dcqmem_adr_i or tag_v) begin
|
if ((tag != dcqmem_adr_i[31:`OR1200_DCTAGL]) || !tag_v)
|
if ((tag != dcqmem_adr_i_tag) || !tag_v)
|
tagcomp_miss = 1'b1;
|
tagcomp_miss = 1'b1;
|
else
|
else
|
tagcomp_miss = 1'b0;
|
tagcomp_miss = 1'b0;
|
end
|
end
|
|
|
| Line 298... |
Line 309... |
.dcqmem_cycstb_i(dcqmem_cycstb_i),
|
.dcqmem_cycstb_i(dcqmem_cycstb_i),
|
.dcqmem_ci_i(dcqmem_ci_i),
|
.dcqmem_ci_i(dcqmem_ci_i),
|
.dcqmem_we_i(dcqmem_we_i),
|
.dcqmem_we_i(dcqmem_we_i),
|
.dcqmem_sel_i(dcqmem_sel_i),
|
.dcqmem_sel_i(dcqmem_sel_i),
|
.tagcomp_miss(tagcomp_miss),
|
.tagcomp_miss(tagcomp_miss),
|
|
.tag(tag),
|
|
.tag_v(tag_v),
|
|
.dirty(dirty),
|
.biudata_valid(dcsb_ack_i),
|
.biudata_valid(dcsb_ack_i),
|
.biudata_error(dcsb_err_i),
|
.biudata_error(dcsb_err_i),
|
.start_addr(dcqmem_adr_i),
|
.lsu_addr(dcqmem_adr_i),
|
.saved_addr(saved_addr),
|
|
.dcram_we(dcram_we),
|
.dcram_we(dcram_we),
|
.biu_read(dcfsm_biu_read),
|
.biu_read(dcfsm_biu_read),
|
.biu_write(dcfsm_biu_write),
|
.biu_write(dcfsm_biu_write),
|
.biu_sel(dcfsm_biu_sel),
|
.dcram_di_sel(dcfsm_dcram_di_sel),
|
|
.biu_do_sel(dcfsm_biu_do_sel),
|
.first_hit_ack(dcfsm_first_hit_ack),
|
.first_hit_ack(dcfsm_first_hit_ack),
|
.first_miss_ack(dcfsm_first_miss_ack),
|
.first_miss_ack(dcfsm_first_miss_ack),
|
.first_miss_err(dcfsm_first_miss_err),
|
.first_miss_err(dcfsm_first_miss_err),
|
.burst(dcfsm_burst),
|
.burst(dcfsm_burst),
|
.tag_we(dcfsm_tag_we),
|
.tag_we(dcfsm_tag_we),
|
.tag_valid(dcfsm_tag_valid),
|
.tag_valid(dcfsm_tag_valid),
|
.dc_addr(dc_addr)
|
.tag_dirty(dcfsm_tag_dirty),
|
|
.dc_addr(dc_addr),
|
|
.dc_no_writethrough(dc_no_writethrough),
|
|
.dc_block_flush(dc_block_flush),
|
|
.dc_block_writeback(dc_block_writeback),
|
|
.spr_dat_i(spr_dat_i),
|
|
.mtspr_dc_done(mtspr_dc_done),
|
|
.spr_cswe(spr_cs & spr_write)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of DC main memory
|
// Instantiation of DC main memory
|
//
|
//
|
| Line 349... |
Line 370... |
.mbist_ctrl_i(mbist_ctrl_i),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
`endif
|
`endif
|
.addr(dctag_addr),
|
.addr(dctag_addr),
|
.en(dctag_en),
|
.en(dctag_en),
|
.we(dctag_we),
|
.we(dctag_we),
|
.datain({dc_addr[31:`OR1200_DCTAGL], dctag_v}),
|
.datain({dc_addr[31:`OR1200_DCTAGL], dctag_v, dctag_dirty}),
|
.tag_v(tag_v),
|
.tag_v(tag_v),
|
.tag(tag)
|
.tag(tag),
|
|
.dirty(dirty)
|
);
|
);
|
|
`endif // !`ifdef OR1200_NO_DC
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
