URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dc_top.v] - Diff between revs 352 and 481

Rev 352	Rev 481
Line 282...	Line 282...

`//`	`//`
`// Select between data generated by DCRAM or passed by BIU`	`// Select between data generated by DCRAM or passed by BIU`
`//`	`//`
`assign dcqmem_dat_o = dcfsm_first_miss_ack \| !dc_en ? dcsb_dat_i : from_dcram;`	`assign dcqmem_dat_o = dcfsm_first_miss_ack \| !dc_en ? dcsb_dat_i : from_dcram;`
`//assign dcqmem_dat_o = !dc_en ? dcsb_dat_i : from_dcram;`

`//`	`//`
`// Tag comparison`	`// Tag comparison`
`//`	`//`
wire [31:`OR1200_DCTAGL] dcqmem_adr_i_tag;	wire [31:`OR1200_DCTAGL] dcqmem_adr_i_tag;