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Line 41... |
//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: or1200_dc_top.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Bugs fixed.
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//
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// Revision 1.8 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.6.4.2 2003/12/09 11:46:48 simons
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// Revision 1.6.4.2 2003/12/09 11:46:48 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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//
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// Revision 1.6.4.1 2003/07/08 15:36:37 lampret
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// Revision 1.6.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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// Added embedded memory QMEM.
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| Line 192... |
Line 199... |
wire [3:0] dcram_we;
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wire [3:0] dcram_we;
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wire dctag_we;
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wire dctag_we;
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wire [31:0] dc_addr;
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wire [31:0] dc_addr;
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wire dcfsm_biu_read;
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wire dcfsm_biu_read;
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wire dcfsm_biu_write;
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wire dcfsm_biu_write;
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wire dcfsm_biu_sel;
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reg tagcomp_miss;
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reg tagcomp_miss;
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wire [`OR1200_DCINDXH:`OR1200_DCLS] dctag_addr;
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wire [`OR1200_DCINDXH:`OR1200_DCLS] dctag_addr;
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wire dctag_en;
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wire dctag_en;
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wire dctag_v;
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wire dctag_v;
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wire dc_inv;
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wire dc_inv;
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wire dcfsm_first_hit_ack;
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wire dcfsm_first_hit_ack;
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wire dcfsm_first_miss_ack;
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wire dcfsm_first_miss_ack;
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wire dcfsm_first_miss_err;
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wire dcfsm_first_miss_err;
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wire dcfsm_burst;
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wire dcfsm_burst;
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wire dcfsm_tag_we;
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wire dcfsm_tag_we;
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wire dcfsm_tag_valid;
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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//
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//
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// RAM BIST
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// RAM BIST
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//
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//
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wire mbist_ram_so;
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wire mbist_ram_so;
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| Line 221... |
Line 230... |
assign dcsb_adr_o = dc_addr;
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assign dcsb_adr_o = dc_addr;
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assign dc_inv = spr_cs & spr_write;
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assign dc_inv = spr_cs & spr_write;
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assign dctag_we = dcfsm_tag_we | dc_inv;
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assign dctag_we = dcfsm_tag_we | dc_inv;
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assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
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assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
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assign dctag_en = dc_inv | dc_en;
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assign dctag_en = dc_inv | dc_en;
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assign dctag_v = ~dc_inv;
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//assign dctag_v = ~dc_inv;
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assign dctag_v = dc_inv ? 1'b0 : dcfsm_tag_valid;
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//
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//
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// Data to BIU is from DCRAM when DC is enabled or from LSU when
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// Data to BIU is from DCRAM when DC is enabled or from LSU when
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// DC is disabled
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// DC is disabled
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//
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//
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| Line 235... |
Line 245... |
// Bypases of the DC when DC is disabled
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// Bypases of the DC when DC is disabled
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//
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//
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assign dcsb_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
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assign dcsb_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
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assign dcsb_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
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assign dcsb_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
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assign dcsb_we_o = (dc_en) ? dcfsm_biu_write : dcqmem_we_i;
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assign dcsb_we_o = (dc_en) ? dcfsm_biu_write : dcqmem_we_i;
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assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcqmem_ci_i) ? 4'b1111 : dcqmem_sel_i;
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//assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcqmem_ci_i) ? 4'b1111 : dcqmem_sel_i;
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assign dcsb_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
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assign dcsb_sel_o = (dc_en & dcfsm_burst) ? 4'b1111 : dcqmem_sel_i;
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//assign dcsb_cab_o = (dc_en) ? dcsb_cyc_o & dcfsm_burst : 1'b0;
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assign dcsb_cab_o = dc_en & dcfsm_burst & dcsb_cyc_o;
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assign dcqmem_rty_o = ~dcqmem_ack_o;
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assign dcqmem_rty_o = ~dcqmem_ack_o;
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assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
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assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
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//
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//
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// DC/LSU normal and error termination
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// DC/LSU normal and error termination
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| Line 254... |
Line 266... |
//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcqmem_adr_i;
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//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcqmem_adr_i;
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//
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//
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// Select between input data generated by LSU or by BIU
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// Select between input data generated by LSU or by BIU
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//
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//
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assign to_dcram = (dcfsm_biu_read) ? dcsb_dat_i : dcqmem_dat_i;
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//assign to_dcram = (dcfsm_biu_read) ? dcsb_dat_i : dcqmem_dat_i;
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assign to_dcram = (dcfsm_biu_sel) ? dcsb_dat_i : dcqmem_dat_i;
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//
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//
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// Select between data generated by DCRAM or passed by BIU
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// Select between data generated by DCRAM or passed by BIU
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//
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//
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assign dcqmem_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
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assign dcqmem_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
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//
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//
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// Tag comparison
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// Tag comparison
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//
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//
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always @(tag or saved_addr or tag_v) begin
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//always @(tag or saved_addr or tag_v) begin
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if ((tag != saved_addr[31:`OR1200_DCTAGL]) || !tag_v)
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// if ((tag != saved_addr[31:`OR1200_DCTAGL]) || !tag_v)
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always @(tag or dcqmem_adr_i or tag_v) begin
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if ((tag != dcqmem_adr_i[31:`OR1200_DCTAGL]) || !tag_v)
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tagcomp_miss = 1'b1;
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tagcomp_miss = 1'b1;
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else
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else
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tagcomp_miss = 1'b0;
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tagcomp_miss = 1'b0;
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end
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end
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| Line 290... |
Line 305... |
.start_addr(dcqmem_adr_i),
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.start_addr(dcqmem_adr_i),
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.saved_addr(saved_addr),
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.saved_addr(saved_addr),
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.dcram_we(dcram_we),
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.dcram_we(dcram_we),
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.biu_read(dcfsm_biu_read),
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.biu_read(dcfsm_biu_read),
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.biu_write(dcfsm_biu_write),
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.biu_write(dcfsm_biu_write),
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.biu_sel(dcfsm_biu_sel),
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.first_hit_ack(dcfsm_first_hit_ack),
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.first_hit_ack(dcfsm_first_hit_ack),
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.first_miss_ack(dcfsm_first_miss_ack),
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.first_miss_ack(dcfsm_first_miss_ack),
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.first_miss_err(dcfsm_first_miss_err),
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.first_miss_err(dcfsm_first_miss_err),
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.burst(dcfsm_burst),
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.burst(dcfsm_burst),
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.tag_we(dcfsm_tag_we),
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.tag_we(dcfsm_tag_we),
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.tag_valid(dcfsm_tag_valid),
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.dc_addr(dc_addr)
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.dc_addr(dc_addr)
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);
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);
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//
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//
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// Instantiation of DC main memory
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// Instantiation of DC main memory
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