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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dc_top.v] - Diff between revs 10 and 141

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Rev 10 Rev 141
Line 41... Line 41...
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: or1200_dc_top.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Minor update: 
 
// Bugs fixed. 
 
//
 
// Revision 1.8  2004/04/05 08:29:57  lampret
 
// Merged branch_qmem into main tree.
 
//
// Revision 1.6.4.2  2003/12/09 11:46:48  simons
// Revision 1.6.4.2  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
//
// Revision 1.6.4.1  2003/07/08 15:36:37  lampret
// Revision 1.6.4.1  2003/07/08 15:36:37  lampret
// Added embedded memory QMEM.
// Added embedded memory QMEM.
Line 192... Line 199...
wire    [3:0]                    dcram_we;
wire    [3:0]                    dcram_we;
wire                            dctag_we;
wire                            dctag_we;
wire    [31:0]                   dc_addr;
wire    [31:0]                   dc_addr;
wire                            dcfsm_biu_read;
wire                            dcfsm_biu_read;
wire                            dcfsm_biu_write;
wire                            dcfsm_biu_write;
 
wire                dcfsm_biu_sel;
reg                             tagcomp_miss;
reg                             tagcomp_miss;
wire    [`OR1200_DCINDXH:`OR1200_DCLS]  dctag_addr;
wire    [`OR1200_DCINDXH:`OR1200_DCLS]  dctag_addr;
wire                            dctag_en;
wire                            dctag_en;
wire                            dctag_v;
wire                            dctag_v;
wire                            dc_inv;
wire                            dc_inv;
wire                            dcfsm_first_hit_ack;
wire                            dcfsm_first_hit_ack;
wire                            dcfsm_first_miss_ack;
wire                            dcfsm_first_miss_ack;
wire                            dcfsm_first_miss_err;
wire                            dcfsm_first_miss_err;
wire                            dcfsm_burst;
wire                            dcfsm_burst;
wire                            dcfsm_tag_we;
wire                            dcfsm_tag_we;
 
wire                dcfsm_tag_valid;
`ifdef OR1200_BIST
`ifdef OR1200_BIST
//
//
// RAM BIST
// RAM BIST
//
//
wire                            mbist_ram_so;
wire                            mbist_ram_so;
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assign dcsb_adr_o = dc_addr;
assign dcsb_adr_o = dc_addr;
assign dc_inv = spr_cs & spr_write;
assign dc_inv = spr_cs & spr_write;
assign dctag_we = dcfsm_tag_we | dc_inv;
assign dctag_we = dcfsm_tag_we | dc_inv;
assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
assign dctag_en = dc_inv | dc_en;
assign dctag_en = dc_inv | dc_en;
assign dctag_v = ~dc_inv;
//assign dctag_v = ~dc_inv;
 
assign dctag_v = dc_inv ? 1'b0 : dcfsm_tag_valid;
 
 
//
//
// Data to BIU is from DCRAM when DC is enabled or from LSU when
// Data to BIU is from DCRAM when DC is enabled or from LSU when
// DC is disabled
// DC is disabled
//
//
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// Bypases of the DC when DC is disabled
// Bypases of the DC when DC is disabled
//
//
assign dcsb_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
assign dcsb_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
assign dcsb_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
assign dcsb_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
assign dcsb_we_o = (dc_en) ? dcfsm_biu_write : dcqmem_we_i;
assign dcsb_we_o = (dc_en) ? dcfsm_biu_write : dcqmem_we_i;
assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcqmem_ci_i) ? 4'b1111 : dcqmem_sel_i;
//assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcqmem_ci_i) ? 4'b1111 : dcqmem_sel_i;
assign dcsb_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
assign dcsb_sel_o = (dc_en & dcfsm_burst) ? 4'b1111 : dcqmem_sel_i;
 
//assign dcsb_cab_o = (dc_en) ? dcsb_cyc_o & dcfsm_burst : 1'b0;
 
assign dcsb_cab_o = dc_en & dcfsm_burst & dcsb_cyc_o;
assign dcqmem_rty_o = ~dcqmem_ack_o;
assign dcqmem_rty_o = ~dcqmem_ack_o;
assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
 
 
//
//
// DC/LSU normal and error termination
// DC/LSU normal and error termination
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//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcqmem_adr_i;
//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcqmem_adr_i;
 
 
//
//
// Select between input data generated by LSU or by BIU
// Select between input data generated by LSU or by BIU
//
//
assign to_dcram = (dcfsm_biu_read) ? dcsb_dat_i : dcqmem_dat_i;
//assign to_dcram = (dcfsm_biu_read) ? dcsb_dat_i : dcqmem_dat_i;
 
assign to_dcram = (dcfsm_biu_sel) ? dcsb_dat_i : dcqmem_dat_i;
 
 
//
//
// Select between data generated by DCRAM or passed by BIU
// Select between data generated by DCRAM or passed by BIU
//
//
assign dcqmem_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
assign dcqmem_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
 
 
//
//
// Tag comparison
// Tag comparison
//
//
always @(tag or saved_addr or tag_v) begin
//always @(tag or saved_addr or tag_v) begin
        if ((tag != saved_addr[31:`OR1200_DCTAGL]) || !tag_v)
//      if ((tag != saved_addr[31:`OR1200_DCTAGL]) || !tag_v)
 
always @(tag or dcqmem_adr_i or tag_v) begin
 
        if ((tag != dcqmem_adr_i[31:`OR1200_DCTAGL]) || !tag_v)
                tagcomp_miss = 1'b1;
                tagcomp_miss = 1'b1;
        else
        else
                tagcomp_miss = 1'b0;
                tagcomp_miss = 1'b0;
end
end
 
 
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        .start_addr(dcqmem_adr_i),
        .start_addr(dcqmem_adr_i),
        .saved_addr(saved_addr),
        .saved_addr(saved_addr),
        .dcram_we(dcram_we),
        .dcram_we(dcram_we),
        .biu_read(dcfsm_biu_read),
        .biu_read(dcfsm_biu_read),
        .biu_write(dcfsm_biu_write),
        .biu_write(dcfsm_biu_write),
 
    .biu_sel(dcfsm_biu_sel),
        .first_hit_ack(dcfsm_first_hit_ack),
        .first_hit_ack(dcfsm_first_hit_ack),
        .first_miss_ack(dcfsm_first_miss_ack),
        .first_miss_ack(dcfsm_first_miss_ack),
        .first_miss_err(dcfsm_first_miss_err),
        .first_miss_err(dcfsm_first_miss_err),
        .burst(dcfsm_burst),
        .burst(dcfsm_burst),
        .tag_we(dcfsm_tag_we),
        .tag_we(dcfsm_tag_we),
 
    .tag_valid(dcfsm_tag_valid),
        .dc_addr(dc_addr)
        .dc_addr(dc_addr)
);
);
 
 
//
//
// Instantiation of DC main memory
// Instantiation of DC main memory

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