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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dc_top.v] - Diff between revs 141 and 258

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Line 1... Line 1... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////                                                              ////
 
////  OR1200's Data Cache top level                               ////
 
////  OR1200's Data Cache top level                               ////
 
////                                                              ////
 
////                                                              ////
 
////  This file is part of the OpenRISC 1200 project              ////
 
////  This file is part of the OpenRISC 1200 project              ////
 
////  http://www.opencores.org/cores/or1k/                        ////
 
////  http://opencores.org/project,or1k                           ////
 
////                                                              ////
 
////                                                              ////
 
////  Description                                                 ////
 
////  Description                                                 ////
 
////  Instantiation of all DC blocks.                             ////
 
////  Instantiation of all DC blocks.                             ////
 
////                                                              ////
 
////                                                              ////
 
////  To Do:                                                      ////
 
////  To Do:                                                      ////
 
////   - make it smaller and faster                               ////
 
////   - Test error during line read or write                     ////
 
////                                                              ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////  Author(s):                                                  ////
 
////      - Damjan Lampret, lampret@opencores.org                 ////
 
////      - Damjan Lampret, lampret@opencores.org                 ////
 
 
 
////      - Julius Baxter, julius@opencores.org                   ////
 
////                                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////                                                              ////
 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
 
//// Copyright (C) 2000, 2010 Authors and OPENCORES.ORG           ////
 
////                                                              ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
//// the original copyright notice and the associated disclaimer. ////
Line 39... Line 40... 
//// Public License along with this source; if not, download it   ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
 
 
//
 
//
 
// $Log: or1200_dc_top.v,v $
 
// $Log: or1200_dc_top.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Minor update: 
// Minor update: 
// Bugs fixed. 
// Bugs fixed. 
//
 
//
 
// Revision 1.8  2004/04/05 08:29:57  lampret
 
 
 
// Merged branch_qmem into main tree.
 
 
 
//
 
 
 
// Revision 1.6.4.2  2003/12/09 11:46:48  simons
 
 
 
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
 
 
 
//
 
 
 
// Revision 1.6.4.1  2003/07/08 15:36:37  lampret
 
 
 
// Added embedded memory QMEM.
 
 
 
//
 
 
 
// Revision 1.6  2002/10/17 20:04:40  lampret
 
 
 
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
 
 
 
//
 
 
 
// Revision 1.5  2002/08/18 19:54:47  lampret
 
 
 
// Added store buffer.
 
 
 
//
 
 
 
// Revision 1.4  2002/02/11 04:33:17  lampret
 
 
 
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
 
 
 
//
 
 
 
// Revision 1.3  2002/01/28 01:16:00  lampret
 
 
 
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
 
 
 
//
 
 
 
// Revision 1.2  2002/01/14 06:18:22  lampret
 
 
 
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
 
 
 
//
 
 
 
// Revision 1.1  2002/01/03 08:16:15  lampret
 
 
 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
 
 
 
//
 
 
 
// Revision 1.10  2001/10/21 17:57:16  lampret
 
 
 
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
 
 
 
//
 
 
 
// Revision 1.9  2001/10/14 13:12:09  lampret
 
 
 
// MP3 version.
 
 
 
//
 
 
 
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
 
 
 
// no message
 
 
 
//
 
 
 
// Revision 1.4  2001/08/13 03:36:20  lampret
 
 
 
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
 
 
 
//
 
 
 
// Revision 1.3  2001/08/09 13:39:33  lampret
 
 
 
// Major clean-up.
 
 
 
//
 
 
 
// Revision 1.2  2001/07/22 03:31:53  lampret
 
 
 
// Fixed RAM's oen bug. Cache bypass under development.
 
 
 
//
 
 
 
// Revision 1.1  2001/07/20 00:46:03  lampret
 
 
 
// Development version of RTL. Libraries are missing.
 
 
 
//
 
 
 
//
 
 
 
 
 
 
 
// synopsys translate_off
 
// synopsys translate_off
 
`include "timescale.v"
 
`include "timescale.v"
 
// synopsys translate_on
 
// synopsys translate_on
 
`include "or1200_defines.v"
 
`include "or1200_defines.v"
Line 109... Line 60... 
module or1200_dc_top(
 
module or1200_dc_top(
 
        // Rst, clk and clock control
 
        // Rst, clk and clock control
 
        clk, rst,
 
        clk, rst,
 
 
 
 
 
        // External i/f
 
        // External i/f
 
        dcsb_dat_o, dcsb_adr_o, dcsb_cyc_o, dcsb_stb_o, dcsb_we_o, dcsb_sel_o, dcsb_cab_o,
 
        dcsb_dat_o, dcsb_adr_o, dcsb_cyc_o, dcsb_stb_o, dcsb_we_o, dcsb_sel_o,
 
        dcsb_dat_i, dcsb_ack_i, dcsb_err_i,
 
        dcsb_cab_o, dcsb_dat_i, dcsb_ack_i, dcsb_err_i,
 
 
 
 
 
        // Internal i/f
 
        // Internal i/f
 
        dc_en,
 
        dc_en,
 
        dcqmem_adr_i, dcqmem_cycstb_i, dcqmem_ci_i,
 
        dcqmem_adr_i, dcqmem_cycstb_i, dcqmem_ci_i,
 
        dcqmem_we_i, dcqmem_sel_i, dcqmem_tag_i, dcqmem_dat_i,
 
        dcqmem_we_i, dcqmem_sel_i, dcqmem_tag_i, dcqmem_dat_i,
 
        dcqmem_dat_o, dcqmem_ack_o, dcqmem_rty_o, dcqmem_err_o, dcqmem_tag_o,
 
        dcqmem_dat_o, dcqmem_ack_o, dcqmem_rty_o, dcqmem_err_o, dcqmem_tag_o,
 
 
 
 
 
 
 
        dc_no_writethrough,
 
 
 
 
 
`ifdef OR1200_BIST
 
`ifdef OR1200_BIST
 
        // RAM BIST
 
        // RAM BIST
 
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
 
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
 
`endif
 
`endif
 
 
 
 
 
        // SPRs
 
        // SPRs
 
        spr_cs, spr_write, spr_dat_i
 
        spr_cs, spr_write, spr_dat_i, spr_addr, mtspr_dc_done
 
);
 
);
 
 
 
 
 
parameter dw = `OR1200_OPERAND_WIDTH;
 
parameter dw = `OR1200_OPERAND_WIDTH;
 
 
 
parameter aw = `OR1200_OPERAND_WIDTH;
 
 
 
 
 
//
 
//
 
// I/O
 
// I/O
 
//
 
//
 
 
 
 
Line 170... Line 124... 
output                          dcqmem_ack_o;
 
output                          dcqmem_ack_o;
 
output                          dcqmem_rty_o;
 
output                          dcqmem_rty_o;
 
output                          dcqmem_err_o;
 
output                          dcqmem_err_o;
 
output  [3:0]                    dcqmem_tag_o;
 
output  [3:0]                    dcqmem_tag_o;
 
 
 
 
 
 
 
input                           dc_no_writethrough;
 
 
 
 
 
`ifdef OR1200_BIST
 
`ifdef OR1200_BIST
 
//
 
//
 
// RAM BIST
 
// RAM BIST
 
//
 
//
 
input mbist_si_i;
 
input mbist_si_i;
Line 185... Line 141... 
// SPR access
 
// SPR access
 
//
 
//
 
input                           spr_cs;
 
input                           spr_cs;
 
input                           spr_write;
 
input                           spr_write;
 
input   [31:0]                   spr_dat_i;
 
input   [31:0]                   spr_dat_i;
 
 
 
input   [aw-1:0]         spr_addr;
 
 
 
output                          mtspr_dc_done;
 
 
 
 
 
 
 
`ifdef OR1200_NO_DC
 
 
 
 
 
 
 
// Bypass cache
 
 
 
 
 
 
 
// IF to external memory
 
 
 
assign dcsb_dat_o = dcqmem_dat_i;
 
 
 
assign dcsb_adr_o = dcqmem_adr_i;
 
 
 
assign dcsb_cyc_o = dcqmem_cycstb_i;
 
 
 
assign dcsb_stb_o = dcqmem_cycstb_i;
 
 
 
assign dcsb_we_o = dcqmem_we_i;
 
 
 
assign dcsb_sel_o = dcqmem_sel_i;
 
 
 
assign dcsb_cab_o = 1'b0;
 
 
 
 
 
 
 
// IF to internal memory
 
 
 
assign dcqmem_dat_o = dcsb_dat_i;
 
 
 
assign dcqmem_ack_o = dcsb_ack_i;
 
 
 
assign dcqmem_err_o = dcsb_err_i;
 
 
 
assign dcqmem_rty_o = ~dcqmem_ack_o;
 
 
 
assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
 
 
 
 
 
 
 
assign mtspr_dc_done = 1'b1;
 
 
 
 
 
 
 
`else
 
 
 
 
 
//
 
//
 
// Internal wires and regs
 
// Internal wires and regs
 
//
 
//
 
wire                            tag_v;
 
wire                            tag_v;
 
wire    [`OR1200_DCTAG_W-2:0]    tag;
 
wire    [`OR1200_DCTAG_W-2:0]    tag;
 
 
 
wire                            dirty;
 
wire    [dw-1:0]         to_dcram;
 
wire    [dw-1:0]         to_dcram;
 
wire    [dw-1:0]         from_dcram;
 
wire    [dw-1:0]         from_dcram;
 
wire    [31:0]                   saved_addr;
 
 
 
wire    [3:0]                    dcram_we;
 
wire    [3:0]                    dcram_we;
 
wire                            dctag_we;
 
wire                            dctag_we;
 
wire    [31:0]                   dc_addr;
 
wire    [31:0]                   dc_addr;
 
wire                            dcfsm_biu_read;
 
wire                            dcfsm_biu_read;
 
wire                            dcfsm_biu_write;
 
wire                            dcfsm_biu_write;
 
wire                dcfsm_biu_sel;
 
wire                            dcfsm_dcram_di_sel;
 
 
 
wire                            dcfsm_biu_do_sel;
 
reg                             tagcomp_miss;
 
reg                             tagcomp_miss;
 
wire    [`OR1200_DCINDXH:`OR1200_DCLS]  dctag_addr;
 
wire    [`OR1200_DCINDXH:`OR1200_DCLS]  dctag_addr;
 
wire                            dctag_en;
 
wire                            dctag_en;
 
wire                            dctag_v;
 
wire                            dctag_v;
 
wire                            dc_inv;
 
wire                            dctag_dirty;
 
 
 
 
 
 
 
wire                            dc_block_invalidate;
 
 
 
wire                            dc_block_flush;
 
 
 
wire                            dc_block_writeback;
 
wire                            dcfsm_first_hit_ack;
 
wire                            dcfsm_first_hit_ack;
 
wire                            dcfsm_first_miss_ack;
 
wire                            dcfsm_first_miss_ack;
 
wire                            dcfsm_first_miss_err;
 
wire                            dcfsm_first_miss_err;
 
wire                            dcfsm_burst;
 
wire                            dcfsm_burst;
 
wire                            dcfsm_tag_we;
 
wire                            dcfsm_tag_we;
 
wire                dcfsm_tag_valid;
 
wire                dcfsm_tag_valid;
 
 
 
wire                            dcfsm_tag_dirty;
 
 
 
 
 
`ifdef OR1200_BIST
 
`ifdef OR1200_BIST
 
//
 
//
 
// RAM BIST
 
// RAM BIST
 
//
 
//
 
wire                            mbist_ram_so;
 
wire                            mbist_ram_so;
Line 222... Line 211... 
wire                            mbist_ram_si = mbist_si_i;
 
wire                            mbist_ram_si = mbist_si_i;
 
wire                            mbist_tag_si = mbist_ram_so;
 
wire                            mbist_tag_si = mbist_ram_so;
 
assign                          mbist_so_o = mbist_tag_so;
 
assign                          mbist_so_o = mbist_tag_so;
 
`endif
 
`endif
 
 
 
 
 
 
 
// Address out to external bus - always from FSM   
 
 
assign dcsb_adr_o = dc_addr;
 
//
 
//
 
// Simple assignments
 
// SPR register decodes
 
//
 
//
 
assign dcsb_adr_o = dc_addr;
 
`ifdef OR1200_DC_WRITETHROUGH
 
assign dc_inv = spr_cs & spr_write;
 
assign dc_block_invalidate = spr_cs & spr_write &
 
assign dctag_we = dcfsm_tag_we | dc_inv;
 
       ((spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBIR) |
 
assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
 
        (spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBFR));
 
assign dctag_en = dc_inv | dc_en;
 
assign dc_block_flush = 0;
 
//assign dctag_v = ~dc_inv;
 
assign dc_block_writeback = 0;
 
assign dctag_v = dc_inv ? 1'b0 : dcfsm_tag_valid;
 
`else
 
 
 
assign dc_block_invalidate = spr_cs & spr_write &
 
 
 
          (spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBIR);
 
 
 
assign dc_block_flush =    spr_cs & spr_write &
 
 
 
           (spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBFR);
 
 
 
assign dc_block_writeback =    spr_cs & spr_write &
 
 
 
           (spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBWR);
 
 
 
`endif // !`ifdef OR1200_DC_WRITETHROUGH
 
 
 
 
 
 
 
assign dctag_we = dcfsm_tag_we | dc_block_invalidate;
 
 
 
assign dctag_addr = dc_block_invalidate ?
 
 
 
                    spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] :
 
 
 
                    dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
 
 
 
assign dctag_en = dc_block_invalidate | dc_en;
 
 
 
 
 
 
 
assign dctag_v = dc_block_invalidate ? 1'b0 : dcfsm_tag_valid;
 
 
 
assign dctag_dirty = dc_block_invalidate ? 1'b0 : dcfsm_tag_dirty;
 
 
 
 
 
//
 
//
 
// Data to BIU is from DCRAM when DC is enabled or from LSU when
 
// Data to BIU is from DCRAM when bursting lines back into memory
 
// DC is disabled
 
 
 
//
 
//
 
assign dcsb_dat_o = dcqmem_dat_i;
 
assign dcsb_dat_o = dcfsm_biu_do_sel ? from_dcram : dcqmem_dat_i;
 
 
 
 
 
 
 
 
 
//
 
//
 
// Bypases of the DC when DC is disabled
 
// Bypases of the DC when DC is disabled
 
//
 
//
 
assign dcsb_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
 
assign dcsb_cyc_o = (dc_en) ?
 
assign dcsb_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
 
                    dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
 
assign dcsb_we_o = (dc_en) ? dcfsm_biu_write : dcqmem_we_i;
 
 
 
//assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcqmem_ci_i) ? 4'b1111 : dcqmem_sel_i;
 
assign dcsb_stb_o = (dc_en) ?
 
assign dcsb_sel_o = (dc_en & dcfsm_burst) ? 4'b1111 : dcqmem_sel_i;
 
                    dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
 
//assign dcsb_cab_o = (dc_en) ? dcsb_cyc_o & dcfsm_burst : 1'b0;
 
 
 
 
 
assign dcsb_we_o = (dc_en) ?
 
 
 
                   dcfsm_biu_write : dcqmem_we_i;
 
 
 
 
 
 
 
assign dcsb_sel_o = (dc_en & dcfsm_burst) ?
 
 
 
                    4'b1111 : dcqmem_sel_i;
 
 
 
 
 
assign dcsb_cab_o = dc_en & dcfsm_burst & dcsb_cyc_o;
 
assign dcsb_cab_o = dc_en & dcfsm_burst & dcsb_cyc_o;
 
assign dcqmem_rty_o = ~dcqmem_ack_o;
 
assign dcqmem_rty_o = ~dcqmem_ack_o;
 
assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
 
assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
 
 
 
 
 
//
 
//
 
// DC/LSU normal and error termination
 
// DC/LSU normal and error termination
 
//
 
//
 
assign dcqmem_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcsb_ack_i;
 
assign dcqmem_ack_o = dc_en ?
 
assign dcqmem_err_o = dc_en ? dcfsm_first_miss_err : dcsb_err_i;
 
                      dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcsb_ack_i;
 
 
 
 
 
//
 
assign dcqmem_err_o = dc_en ? dcfsm_first_miss_err : dcsb_err_i;
 
// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
 
 
 
//
 
 
 
//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcqmem_adr_i;
 
 
 
 
 
 
 
//
 
//
 
// Select between input data generated by LSU or by BIU
 
// Select between input data generated by LSU or by BIU
 
//
 
//
 
//assign to_dcram = (dcfsm_biu_read) ? dcsb_dat_i : dcqmem_dat_i;
 
assign to_dcram = (dcfsm_dcram_di_sel) ? dcsb_dat_i : dcqmem_dat_i;
 
assign to_dcram = (dcfsm_biu_sel) ? dcsb_dat_i : dcqmem_dat_i;
 
 
 
 
 
 
 
//
 
//
 
// Select between data generated by DCRAM or passed by BIU
 
// Select between data generated by DCRAM or passed by BIU
 
//
 
//
 
assign dcqmem_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
 
assign dcqmem_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
 
 
 
//assign dcqmem_dat_o = !dc_en ? dcsb_dat_i : from_dcram;
 
 
 
 
 
//
 
//
 
// Tag comparison
 
// Tag comparison
 
//
 
//
 
//always @(tag or saved_addr or tag_v) begin
 
   wire [31:`OR1200_DCTAGL]  dcqmem_adr_i_tag;
 
//      if ((tag != saved_addr[31:`OR1200_DCTAGL]) || !tag_v)
 
   assign dcqmem_adr_i_tag = dcqmem_adr_i[31:`OR1200_DCTAGL];
 
 
 
 
 
always @(tag or dcqmem_adr_i or tag_v) begin
 
always @(tag or dcqmem_adr_i or tag_v) begin
 
        if ((tag != dcqmem_adr_i[31:`OR1200_DCTAGL]) || !tag_v)
 
        if ((tag != dcqmem_adr_i_tag) || !tag_v)
 
                tagcomp_miss = 1'b1;
 
                tagcomp_miss = 1'b1;
 
        else
 
        else
 
                tagcomp_miss = 1'b0;
 
                tagcomp_miss = 1'b0;
 
end
 
end
 
 
 
 
Line 298... Line 309... 
        .dcqmem_cycstb_i(dcqmem_cycstb_i),
 
        .dcqmem_cycstb_i(dcqmem_cycstb_i),
 
        .dcqmem_ci_i(dcqmem_ci_i),
 
        .dcqmem_ci_i(dcqmem_ci_i),
 
        .dcqmem_we_i(dcqmem_we_i),
 
        .dcqmem_we_i(dcqmem_we_i),
 
        .dcqmem_sel_i(dcqmem_sel_i),
 
        .dcqmem_sel_i(dcqmem_sel_i),
 
        .tagcomp_miss(tagcomp_miss),
 
        .tagcomp_miss(tagcomp_miss),
 
 
 
        .tag(tag),
 
 
 
        .tag_v(tag_v),
 
 
 
        .dirty(dirty),
 
        .biudata_valid(dcsb_ack_i),
 
        .biudata_valid(dcsb_ack_i),
 
        .biudata_error(dcsb_err_i),
 
        .biudata_error(dcsb_err_i),
 
        .start_addr(dcqmem_adr_i),
 
        .lsu_addr(dcqmem_adr_i),
 
        .saved_addr(saved_addr),
 
 
 
        .dcram_we(dcram_we),
 
        .dcram_we(dcram_we),
 
        .biu_read(dcfsm_biu_read),
 
        .biu_read(dcfsm_biu_read),
 
        .biu_write(dcfsm_biu_write),
 
        .biu_write(dcfsm_biu_write),
 
    .biu_sel(dcfsm_biu_sel),
 
        .dcram_di_sel(dcfsm_dcram_di_sel),
 
 
 
        .biu_do_sel(dcfsm_biu_do_sel),
 
        .first_hit_ack(dcfsm_first_hit_ack),
 
        .first_hit_ack(dcfsm_first_hit_ack),
 
        .first_miss_ack(dcfsm_first_miss_ack),
 
        .first_miss_ack(dcfsm_first_miss_ack),
 
        .first_miss_err(dcfsm_first_miss_err),
 
        .first_miss_err(dcfsm_first_miss_err),
 
        .burst(dcfsm_burst),
 
        .burst(dcfsm_burst),
 
        .tag_we(dcfsm_tag_we),
 
        .tag_we(dcfsm_tag_we),
 
    .tag_valid(dcfsm_tag_valid),
 
    .tag_valid(dcfsm_tag_valid),
 
        .dc_addr(dc_addr)
 
        .tag_dirty(dcfsm_tag_dirty),
 
 
 
        .dc_addr(dc_addr),
 
 
 
        .dc_no_writethrough(dc_no_writethrough),
 
 
 
        .dc_block_flush(dc_block_flush),
 
 
 
        .dc_block_writeback(dc_block_writeback),
 
 
 
        .spr_dat_i(spr_dat_i),
 
 
 
        .mtspr_dc_done(mtspr_dc_done),
 
 
 
        .spr_cswe(spr_cs & spr_write)
 
);
 
);
 
 
 
 
 
//
 
//
 
// Instantiation of DC main memory
 
// Instantiation of DC main memory
 
//
 
//
Line 349... Line 370... 
        .mbist_ctrl_i(mbist_ctrl_i),
 
        .mbist_ctrl_i(mbist_ctrl_i),
 
`endif
 
`endif
 
        .addr(dctag_addr),
 
        .addr(dctag_addr),
 
        .en(dctag_en),
 
        .en(dctag_en),
 
        .we(dctag_we),
 
        .we(dctag_we),
 
        .datain({dc_addr[31:`OR1200_DCTAGL], dctag_v}),
 
        .datain({dc_addr[31:`OR1200_DCTAGL], dctag_v, dctag_dirty}),
 
        .tag_v(tag_v),
 
        .tag_v(tag_v),
 
        .tag(tag)
 
        .tag(tag),
 
 
 
        .dirty(dirty)
 
);
 
);
 
 
 
`endif // !`ifdef OR1200_NO_DC
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
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