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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 259 and 358

Rev 259	Rev 358
Line 173...	Line 173...
`//`	`//`
`// Do not change below unless you know what you are doing`	`// Do not change below unless you know what you are doing`
`//`	`//`

`//`	`//`
	`// Reset active low`
	`//`
	//`define OR1200_RST_ACT_LOW

	`//`
`// Enable RAM BIST`	`// Enable RAM BIST`
`//`	`//`
`// At the moment this only works for Virtual Silicon`	`// At the moment this only works for Virtual Silicon`
`// single port RAMs. For other RAMs it has not effect.`	`// single port RAMs. For other RAMs it has not effect.`
`// Special wrapper for VS RAMs needs to be provided`	`// Special wrapper for VS RAMs needs to be provided`
Line 424...	Line 429...
`//`	`//`
`define OR1200_IMPL_MEM2REG1	`define OR1200_IMPL_MEM2REG1
//`define OR1200_IMPL_MEM2REG2	//`define OR1200_IMPL_MEM2REG2

`//`	`//`
	`// Reset value and event`
	`//`
	`ifdef OR1200_RST_ACT_LOW
	`define OR1200_RST_VALUE (1'b0)
	`define OR1200_RST_EVENT negedge
	`else
	`define OR1200_RST_VALUE (1'b1)
	`define OR1200_RST_EVENT posedge
	`endif

	`//`
`// ALUOPs`	`// ALUOPs`
`//`	`//`
`define OR1200_ALUOP_WIDTH 4	`define OR1200_ALUOP_WIDTH 4
`define OR1200_ALUOP_NOP 4'd4	`define OR1200_ALUOP_NOP 4'd4
`/* Order defined by arith insns that have two source operands both in regs`	`/* Order defined by arith insns that have two source operands both in regs`