| Line 161... |
Line 161... |
// (consider available FPGA memory resources)
|
// (consider available FPGA memory resources)
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//
|
//
|
//`define OR1200_IC_1W_512B
|
//`define OR1200_IC_1W_512B
|
//`define OR1200_IC_1W_4KB
|
//`define OR1200_IC_1W_4KB
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`define OR1200_IC_1W_8KB
|
`define OR1200_IC_1W_8KB
|
|
//`define OR1200_IC_1W_16KB
|
|
//`define OR1200_IC_1W_32KB
|
//`define OR1200_DC_1W_4KB
|
//`define OR1200_DC_1W_4KB
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`define OR1200_DC_1W_8KB
|
`define OR1200_DC_1W_8KB
|
|
//`define OR1200_DC_1W_16KB
|
|
//`define OR1200_DC_1W_32KB
|
|
|
`endif
|
`endif
|
|
|
|
|
//////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////
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| Line 358... |
Line 362... |
|
|
//
|
//
|
// Implement multiply-and-accumulate
|
// Implement multiply-and-accumulate
|
//
|
//
|
// By default MAC is implemented. To
|
// By default MAC is implemented. To
|
// implement MAC, multiplier needs to be
|
// implement MAC, multiplier (non-serial) needs to be
|
// implemented.
|
// implemented.
|
//
|
//
|
`define OR1200_MAC_IMPLEMENTED
|
//`define OR1200_MAC_IMPLEMENTED
|
|
|
//
|
//
|
// Implement optional l.div/l.divu instructions
|
// Implement optional l.div/l.divu instructions
|
//
|
//
|
// By default divide instructions are not implemented
|
// By default divide instructions are not implemented
|
// to save area and increase clock frequency. or32 C/C++
|
// to save area.
|
// compiler can use soft library for division.
|
|
//
|
//
|
// To implement divide, both multiplier and MAC needs to be implemented.
|
|
//
|
//
|
`define OR1200_DIV_IMPLEMENTED
|
`define OR1200_DIV_IMPLEMENTED
|
|
|
//
|
//
|
// Low power, slower multiplier
|
// Serial multiplier.
|
|
//
|
|
//`define OR1200_MULT_SERIAL
|
|
|
//
|
//
|
// Select between low-power (larger) multiplier
|
// Serial divider.
|
// and faster multiplier. The actual difference
|
// Uncomment to use a serial divider, otherwise will
|
// is only AND logic that prevents distribution
|
// be a generic parallel implementation.
|
// of operands into the multiplier when instruction
|
|
// in execution is not multiply instruction
|
|
//
|
//
|
//`define OR1200_LOWPWR_MULT
|
`define OR1200_DIV_SERIAL
|
|
|
//
|
//
|
// Implement HW Single Precision FPU
|
// Implement HW Single Precision FPU
|
//
|
//
|
//`define OR1200_FPU_IMPLEMENTED
|
//`define OR1200_FPU_IMPLEMENTED
|
//
|
|
|
|
//
|
//
|
// Clock ratio RISC clock versus WB clock
|
// Clock ratio RISC clock versus WB clock
|
//
|
//
|
// If you plan to run WB:RISC clock fixed to 1:1, disable
|
// If you plan to run WB:RISC clock fixed to 1:1, disable
|
| Line 462... |
Line 465... |
`define OR1200_ALUOP_MUL 4'd6
|
`define OR1200_ALUOP_MUL 4'd6
|
`define OR1200_ALUOP_CUST5 4'd7
|
`define OR1200_ALUOP_CUST5 4'd7
|
`define OR1200_ALUOP_SHROT 4'd8
|
`define OR1200_ALUOP_SHROT 4'd8
|
`define OR1200_ALUOP_DIV 4'd9
|
`define OR1200_ALUOP_DIV 4'd9
|
`define OR1200_ALUOP_DIVU 4'd10
|
`define OR1200_ALUOP_DIVU 4'd10
|
/* Order not specifically defined. */
|
`define OR1200_ALUOP_MULU 4'd11
|
`define OR1200_ALUOP_IMM 4'd11
|
/* Values sent to ALU from decode unit - not strictly defined by ISA */
|
`define OR1200_ALUOP_MOVHI 4'd12
|
`define OR1200_ALUOP_MOVHI 4'd12
|
`define OR1200_ALUOP_COMP 4'd13
|
`define OR1200_ALUOP_COMP 4'd13
|
`define OR1200_ALUOP_MTSR 4'd14
|
`define OR1200_ALUOP_MTSR 4'd14
|
`define OR1200_ALUOP_MFSR 4'd15
|
`define OR1200_ALUOP_MFSR 4'd15
|
`define OR1200_ALUOP_CMOV 4'd14
|
`define OR1200_ALUOP_CMOV 4'd14
|
| Line 1023... |
Line 1026... |
|
|
// Define it if you want PIC implemented
|
// Define it if you want PIC implemented
|
`define OR1200_PIC_IMPLEMENTED
|
`define OR1200_PIC_IMPLEMENTED
|
|
|
// Define number of interrupt inputs (2-31)
|
// Define number of interrupt inputs (2-31)
|
`define OR1200_PIC_INTS 31
|
`define OR1200_PIC_INTS 20
|
|
|
// Address offsets of PIC registers inside PIC group
|
// Address offsets of PIC registers inside PIC group
|
`define OR1200_PIC_OFS_PICMR 2'd0
|
`define OR1200_PIC_OFS_PICMR 2'd0
|
`define OR1200_PIC_OFS_PICSR 2'd2
|
`define OR1200_PIC_OFS_PICSR 2'd2
|
|
|
| Line 1218... |
Line 1221... |
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
//
|
//
|
// Insn cache (IC)
|
// Insn cache (IC)
|
//
|
//
|
|
|
// 3 for 8 bytes, 4 for 16 bytes etc
|
// 4 for 16 byte line, 5 for 32 byte lines.
|
|
`ifdef OR1200_IC_1W_32KB
|
|
`define OR1200_ICLS 5
|
|
`else
|
`define OR1200_ICLS 4
|
`define OR1200_ICLS 4
|
|
`endif
|
|
|
//
|
//
|
// IC configurations
|
// IC configurations
|
//
|
//
|
`ifdef OR1200_IC_1W_512B
|
`ifdef OR1200_IC_1W_512B
|
| Line 1248... |
Line 1255... |
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12
|
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12
|
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13
|
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13
|
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9
|
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9
|
`define OR1200_ICTAG_W 20
|
`define OR1200_ICTAG_W 20
|
`endif
|
`endif
|
|
`ifdef OR1200_IC_1W_16KB
|
|
`define OR1200_ICSIZE 14 // 16384
|
|
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 12
|
|
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 13
|
|
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14
|
|
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10
|
|
`define OR1200_ICTAG_W 19
|
|
`endif
|
|
`ifdef OR1200_IC_1W_32KB
|
|
`define OR1200_ICSIZE 15 // 32768
|
|
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 13
|
|
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 14
|
|
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14
|
|
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10
|
|
`define OR1200_ICTAG_W 18
|
|
`endif
|
|
|
|
|
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
//
|
//
|
// Data cache (DC)
|
// Data cache (DC)
|
//
|
//
|
|
|
// 3 for 8 bytes, 4 for 16 bytes etc
|
// 4 for 16 bytes, 5 for 32 bytes
|
|
`ifdef OR1200_DC_1W_32KB
|
|
`define OR1200_DCLS 5
|
|
`else
|
`define OR1200_DCLS 4
|
`define OR1200_DCLS 4
|
|
`endif
|
|
|
// Define to enable default behavior of cache as write through
|
// Define to enable default behavior of cache as write through
|
// Turning this off enabled write back statergy
|
// Turning this off enabled write back statergy
|
//
|
//
|
`define OR1200_DC_WRITETHROUGH
|
`define OR1200_DC_WRITETHROUGH
|
| Line 1296... |
Line 1323... |
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12
|
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12
|
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
|
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
|
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
|
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
|
`define OR1200_DCTAG_W 20
|
`define OR1200_DCTAG_W 20
|
`endif
|
`endif
|
|
`ifdef OR1200_DC_1W_16KB
|
|
`define OR1200_DCSIZE 14 // 16384
|
|
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 12
|
|
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 13
|
|
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 14
|
|
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10
|
|
`define OR1200_DCTAG_W 19
|
|
`endif
|
|
`ifdef OR1200_DC_1W_32KB
|
|
`define OR1200_DCSIZE 15 // 32768
|
|
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 13
|
|
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 14
|
|
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 15
|
|
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10
|
|
`define OR1200_DCTAG_W 18
|
|
`endif
|
|
|
|
|
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
//
|
//
|
// Store buffer (SB)
|
// Store buffer (SB)
|
| Line 1719... |
Line 1762... |
`endif
|
`endif
|
`define OR1200_DCFGR_RES1 27'd0
|
`define OR1200_DCFGR_RES1 27'd0
|
|
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
// Boot Address Selection //
|
// Boot Address Selection //
|
// This only changes where the initial reset occurs. EPH setting is still //
|
// //
|
// used to determine where vectors are located. //
|
// Allows a definable boot address, potentially different to the usual reset //
|
|
// vector to allow for power-on code to be run, if desired. //
|
|
// //
|
|
// OR1200_BOOT_ADR should be the 32-bit address of the boot location //
|
|
// OR1200_BOOT_PCREG_DEFAULT should be ((OR1200_BOOT_ADR-4)>>2) //
|
|
// //
|
|
// For default reset behavior uncomment the settings under the "Boot 0x100" //
|
|
// comment below. //
|
|
// //
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
// Boot from 0xf0000100
|
// Boot from 0xf0000100
|
//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
|
//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
|
//`define OR1200_BOOT_ADR 32'hf0000100
|
//`define OR1200_BOOT_ADR 32'hf0000100
|
// Boot from 0x100
|
// Boot from 0x100
|
