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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 10 and 141

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////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: or1200_defines.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Minor update: 
 
// Defines added, bugs fixed. 
 
//
 
// Revision 1.45  2006/04/09 01:32:29  lampret
 
// See OR1200_MAC_SHIFTBY in or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts.
 
//
// Revision 1.44  2005/10/19 11:37:56  jcastillo
// Revision 1.44  2005/10/19 11:37:56  jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
//
// Revision 1.43  2005/01/07 09:23:39  andreje
// Revision 1.43  2005/01/07 09:23:39  andreje
// l.ff1 and l.cmov instructions added
// l.ff1 and l.cmov instructions added
Line 323... Line 330...
//`define OR1200_ALTERA_LPM
//`define OR1200_ALTERA_LPM
//`define OR1200_XILINX_RAMB16
//`define OR1200_XILINX_RAMB16
//`define OR1200_XILINX_RAMB4
//`define OR1200_XILINX_RAMB4
//`define OR1200_XILINX_RAM32X1D
//`define OR1200_XILINX_RAM32X1D
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
 
`define OR1200_ACTEL
 
 
//
//
// Do not implement Data cache
// Do not implement Data cache
//
//
`define OR1200_NO_DC
`define OR1200_NO_DC
 
 
//
//
// Do not implement Insn cache
// Do not implement Insn cache
//
//
`define OR1200_NO_IC
//`define OR1200_NO_IC
 
 
//
//
// Do not implement Data MMU
// Do not implement Data MMU
//
//
`define OR1200_NO_DMMU
//`define OR1200_NO_DMMU
 
 
//
//
// Do not implement Insn MMU
// Do not implement Insn MMU
//
//
`define OR1200_NO_IMMU
//`define OR1200_NO_IMMU
 
 
//
//
// Select between ASIC and generic multiplier
// Select between ASIC and generic multiplier
//
//
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
Line 357... Line 365...
//
//
// Size/type of insn/data cache if implemented
// Size/type of insn/data cache if implemented
// (consider available FPGA memory resources)
// (consider available FPGA memory resources)
//
//
//`define OR1200_IC_1W_512B
//`define OR1200_IC_1W_512B
`define OR1200_IC_1W_4KB
//`define OR1200_IC_1W_4KB
//`define OR1200_IC_1W_8KB
`define OR1200_IC_1W_8KB
`define OR1200_DC_1W_4KB
`define OR1200_DC_1W_4KB
//`define OR1200_DC_1W_8KB
//`define OR1200_DC_1W_8KB
 
 
`endif
`endif
 
 
Line 422... Line 430...
// to identify bursts. It is no longer needed but
// to identify bursts. It is no longer needed but
// remains enabled for compatibility with old designs.
// remains enabled for compatibility with old designs.
//
//
// To remove *wb_cab_o ports undefine this macro.
// To remove *wb_cab_o ports undefine this macro.
//
//
`define OR1200_WB_CAB
//`define OR1200_WB_CAB
 
 
//
//
// WISHBONE B3 compatible interface
// WISHBONE B3 compatible interface
//
//
// This follows the WISHBONE B3 specification.
// This follows the WISHBONE B3 specification.
Line 434... Line 442...
// designs still don't use WB b3.
// designs still don't use WB b3.
//
//
// To enable *wb_cti_o/*wb_bte_o ports,
// To enable *wb_cti_o/*wb_bte_o ports,
// define this macro.
// define this macro.
//
//
//`define OR1200_WB_B3
`define OR1200_WB_B3
 
 
 
//
 
// LOG all WISHBONE accesses
 
//
 
`define OR1200_LOG_WB_ACCESS
 
 
//
//
// Enable additional synthesis directives if using
// Enable additional synthesis directives if using
// _Synopsys_ synthesis tool
// _Synopsys_ synthesis tool
//
//
Line 481... Line 494...
// By default implementation of l.addc/l.addic
// By default implementation of l.addc/l.addic
// instructions is enabled in case you need them.
// instructions is enabled in case you need them.
// If you don't use them, then disable implementation
// If you don't use them, then disable implementation
// to save area.
// to save area.
//
//
`define OR1200_IMPL_ADDC
//`define OR1200_IMPL_ADDC
 
 
 
//
 
// Implement l.sub instruction
 
//
 
// By default implementation of l.sub instructions
 
// is enabled to be compliant with the simulator.
 
// If you don't use carry bit, then disable
 
// implementation to save area.
 
//
 
`define OR1200_IMPL_SUB
 
 
//
//
// Implement carry bit SR[CY]
// Implement carry bit SR[CY]
//
//
 
//
// By default implementation of SR[CY] is enabled
// By default implementation of SR[CY] is enabled
// to be compliant with the simulator. However
// to be compliant with the simulator. However SR[CY]
// SR[CY] is explicitly only used by l.addc/l.addic
// is explicitly only used by l.addc/l.addic/l.sub
// instructions and if these two insns are not
// instructions and if these three insns are not
// implemented there is not much point having SR[CY].
// implemented there is not much point having SR[CY].
//
//
`define OR1200_IMPL_CY
//`define OR1200_IMPL_CY
 
 
//
//
// Implement optional l.div/l.divu instructions
// Implement optional l.div/l.divu instructions
//
//
// By default divide instructions are not implemented
// By default divide instructions are not implemented
Line 535... Line 559...
//
//
// Implement multiplier
// Implement multiplier
//
//
// By default multiplier is implemented
// By default multiplier is implemented
//
//
`define OR1200_MULT_IMPLEMENTED
//`define OR1200_MULT_IMPLEMENTED
 
 
//
//
// Implement multiply-and-accumulate
// Implement multiply-and-accumulate
//
//
// By default MAC is implemented. To
// By default MAC is implemented. To
// implement MAC, multiplier needs to be
// implement MAC, multiplier needs to be
// implemented.
// implemented.
//
//
`define OR1200_MAC_IMPLEMENTED
//`define OR1200_MAC_IMPLEMENTED
 
 
//
//
// Low power, slower multiplier
// Low power, slower multiplier
//
//
// Select between low-power (larger) multiplier
// Select between low-power (larger) multiplier
Line 569... Line 593...
// and use clmode to set ratio
// and use clmode to set ratio
//
//
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
// clmode to set ratio
// clmode to set ratio
//
//
`define OR1200_CLKDIV_2_SUPPORTED
//`define OR1200_CLKDIV_2_SUPPORTED
//`define OR1200_CLKDIV_4_SUPPORTED
//`define OR1200_CLKDIV_4_SUPPORTED
 
 
//
//
// Type of register file RAM
// Type of register file RAM
//
//
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
//`define OR1200_RFRAM_TWOPORT
//`define OR1200_RFRAM_TWOPORT
//
//
// Memory macro dual port (see or1200_dpram_32x32.v)
// Memory macro dual port (see or1200_dpram_32x32.v)
//`define OR1200_RFRAM_DUALPORT
`define OR1200_RFRAM_DUALPORT
 
 
//
//
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
`define OR1200_RFRAM_GENERIC
//`define OR1200_RFRAM_GENERIC
 
//  Generic register file supports - 16 registers 
 
`ifdef OR1200_RFRAM_GENERIC
 
//    `define OR1200_RFRAM_16REG
 
`endif
 
 
//
//
// Type of mem2reg aligner to implement.
// Type of mem2reg aligner to implement.
//
//
// Once OR1200_IMPL_MEM2REG2 yielded faster
// Once OR1200_IMPL_MEM2REG2 yielded faster
Line 623... Line 652...
`define OR1200_ALUOP_CMOV 4'd14
`define OR1200_ALUOP_CMOV 4'd14
`define OR1200_ALUOP_FF1  4'd15
`define OR1200_ALUOP_FF1  4'd15
//
//
// MACOPs
// MACOPs
//
//
`define OR1200_MACOP_WIDTH      2
`define OR1200_MACOP_WIDTH      3
`define OR1200_MACOP_NOP        2'b00
`define OR1200_MACOP_NOP        3'b000
`define OR1200_MACOP_MAC        2'b01
`define OR1200_MACOP_MAC        3'b001
`define OR1200_MACOP_MSB        2'b10
`define OR1200_MACOP_MSB        3'b010
 
 
//
//
// Shift/rotate ops
// Shift/rotate ops
//
//
`define OR1200_SHROTOP_WIDTH    2
`define OR1200_SHROTOP_WIDTH    2
Line 682... Line 711...
`define OR1200_LSUOP_SD         4'b1000
`define OR1200_LSUOP_SD         4'b1000
`define OR1200_LSUOP_SB         4'b1010
`define OR1200_LSUOP_SB         4'b1010
`define OR1200_LSUOP_SH         4'b1100
`define OR1200_LSUOP_SH         4'b1100
`define OR1200_LSUOP_SW         4'b1110
`define OR1200_LSUOP_SW         4'b1110
 
 
 
// Number of bits of load/store EA precalculated in ID stage
 
// for balancing ID and EX stages.
 
//
 
// Valid range: 2,3,...,30,31
 
`define OR1200_LSUEA_PRECALC            2
 
 
// FETCHOPs
// FETCHOPs
`define OR1200_FETCHOP_WIDTH            1
`define OR1200_FETCHOP_WIDTH            1
`define OR1200_FETCHOP_NOP              1'b0
`define OR1200_FETCHOP_NOP              1'b0
`define OR1200_FETCHOP_LW               1'b1
`define OR1200_FETCHOP_LW               1'b1
 
 
Line 890... Line 925...
`define OR1200_SPR_ESR          11'd64
`define OR1200_SPR_ESR          11'd64
 
 
//
//
// SR bits
// SR bits
//
//
`define OR1200_SR_WIDTH 16
`define OR1200_SR_WIDTH 17
`define OR1200_SR_SM   0
`define OR1200_SR_SM   0
`define OR1200_SR_TEE  1
`define OR1200_SR_TEE  1
`define OR1200_SR_IEE  2
`define OR1200_SR_IEE  2
`define OR1200_SR_DCE  3
`define OR1200_SR_DCE  3
`define OR1200_SR_ICE  4
`define OR1200_SR_ICE  4
Line 907... Line 942...
`define OR1200_SR_OV   11       // Unused
`define OR1200_SR_OV   11       // Unused
`define OR1200_SR_OVE  12       // Unused
`define OR1200_SR_OVE  12       // Unused
`define OR1200_SR_DSX  13       // Unused
`define OR1200_SR_DSX  13       // Unused
`define OR1200_SR_EPH  14
`define OR1200_SR_EPH  14
`define OR1200_SR_FO   15
`define OR1200_SR_FO   15
 
`define OR1200_SR_TED  16
`define OR1200_SR_CID  31:28    // Unimplemented
`define OR1200_SR_CID  31:28    // Unimplemented
 
 
//
//
// Bits that define offset inside the group
// Bits that define offset inside the group
//
//
Line 928... Line 964...
//
//
// Power Management (PM)
// Power Management (PM)
//
//
 
 
// Define it if you want PM implemented
// Define it if you want PM implemented
`define OR1200_PM_IMPLEMENTED
//`define OR1200_PM_IMPLEMENTED
 
 
// Bit positions inside PMR (don't change)
// Bit positions inside PMR (don't change)
`define OR1200_PM_PMR_SDF 3:0
`define OR1200_PM_PMR_SDF 3:0
`define OR1200_PM_PMR_DME 4
`define OR1200_PM_PMR_DME 4
`define OR1200_PM_PMR_SME 5
`define OR1200_PM_PMR_SME 5
Line 972... Line 1008...
// with or32 gdb)
// with or32 gdb)
//
//
//`define OR1200_DU_HWBKPTS
//`define OR1200_DU_HWBKPTS
 
 
// Number of DVR/DCR pairs if HW breakpoints enabled
// Number of DVR/DCR pairs if HW breakpoints enabled
 
//      Comment / uncomment DU_DVRn / DU_DCRn pairs bellow according to this number ! 
 
//      DU_DVR0..DU_DVR7 should be uncommented for 8 DU_DVRDCR_PAIRS 
`define OR1200_DU_DVRDCR_PAIRS 8
`define OR1200_DU_DVRDCR_PAIRS 8
 
 
// Define if you want trace buffer
// Define if you want trace buffer
 
//      (for now only available for Xilinx Virtex FPGAs)
//`define OR1200_DU_TB_IMPLEMENTED
//`define OR1200_DU_TB_IMPLEMENTED
 
 
 
 
//
//
// Address offsets of DU registers inside DU group
// Address offsets of DU registers inside DU group
//
//
// To not implement a register, doq not define its address
// To not implement a register, doq not define its address
//
//
Line 1103... Line 1143...
 
 
// Define it if you want PIC implemented
// Define it if you want PIC implemented
`define OR1200_PIC_IMPLEMENTED
`define OR1200_PIC_IMPLEMENTED
 
 
// Define number of interrupt inputs (2-31)
// Define number of interrupt inputs (2-31)
`define OR1200_PIC_INTS 20
`define OR1200_PIC_INTS 31
 
 
// Address offsets of PIC registers inside PIC group
// Address offsets of PIC registers inside PIC group
`define OR1200_PIC_OFS_PICMR 2'd0
`define OR1200_PIC_OFS_PICMR 2'd0
`define OR1200_PIC_OFS_PICSR 2'd2
`define OR1200_PIC_OFS_PICSR 2'd2
 
 
Line 1431... Line 1471...
// IMMU/DMMU so all addresses are physical (so the MMUs can be
// IMMU/DMMU so all addresses are physical (so the MMUs can be
// used with QMEM and QMEM is seen by the CPU just like any other
// used with QMEM and QMEM is seen by the CPU just like any other
// memory in the system). IC/DC are sitting behind QMEM so the
// memory in the system). IC/DC are sitting behind QMEM so the
// whole design timing might be worse with QMEM implemented.
// whole design timing might be worse with QMEM implemented.
//
//
`define OR1200_QMEM_IMPLEMENTED
//`define OR1200_QMEM_IMPLEMENTED
 
 
//
//
// Base address and mask of QMEM
// Base address and mask of QMEM
//
//
// Base address defines first address of QMEM. Mask defines
// Base address defines first address of QMEM. Mask defines
Line 1553... Line 1593...
`define OR1200_UPR_DUP                  1'b1
`define OR1200_UPR_DUP                  1'b1
`else
`else
`define OR1200_UPR_DUP                  1'b0
`define OR1200_UPR_DUP                  1'b0
`endif
`endif
`define OR1200_UPR_PCUP                 1'b0    // Performance counters not present
`define OR1200_UPR_PCUP                 1'b0    // Performance counters not present
`ifdef OR1200_DU_IMPLEMENTED
`ifdef OR1200_PM_IMPLEMENTED
`define OR1200_UPR_PMP                  1'b1
`define OR1200_UPR_PMP                  1'b1
`else
`else
`define OR1200_UPR_PMP                  1'b0
`define OR1200_UPR_PMP                  1'b0
`endif
`endif
`ifdef OR1200_DU_IMPLEMENTED
`ifdef OR1200_PIC_IMPLEMENTED
`define OR1200_UPR_PICP                 1'b1
`define OR1200_UPR_PICP                 1'b1
`else
`else
`define OR1200_UPR_PICP                 1'b0
`define OR1200_UPR_PICP                 1'b0
`endif
`endif
`ifdef OR1200_DU_IMPLEMENTED
`ifdef OR1200_TT_IMPLEMENTED
`define OR1200_UPR_TTP                  1'b1
`define OR1200_UPR_TTP                  1'b1
`else
`else
`define OR1200_UPR_TTP                  1'b0
`define OR1200_UPR_TTP                  1'b0
`endif
`endif
`define OR1200_UPR_RES1                 13'h0000
`define OR1200_UPR_RES1                 13'h0000
Line 1583... Line 1623...
`define OR1200_CPUCFGR_OV64S_BITS       9
`define OR1200_CPUCFGR_OV64S_BITS       9
`define OR1200_CPUCFGR_RES1_BITS        31:10
`define OR1200_CPUCFGR_RES1_BITS        31:10
 
 
// CPUCFGR values
// CPUCFGR values
`define OR1200_CPUCFGR_NSGF             4'h0
`define OR1200_CPUCFGR_NSGF             4'h0
 
`ifdef OR1200_RFRAM_16REG
 
    `define OR1200_CPUCFGR_HGF                  1'b1
 
`else
`define OR1200_CPUCFGR_HGF              1'b0
`define OR1200_CPUCFGR_HGF              1'b0
 
`endif
`define OR1200_CPUCFGR_OB32S            1'b1
`define OR1200_CPUCFGR_OB32S            1'b1
`define OR1200_CPUCFGR_OB64S            1'b0
`define OR1200_CPUCFGR_OB64S            1'b0
`define OR1200_CPUCFGR_OF32S            1'b0
`define OR1200_CPUCFGR_OF32S            1'b0
`define OR1200_CPUCFGR_OF64S            1'b0
`define OR1200_CPUCFGR_OF64S            1'b0
`define OR1200_CPUCFGR_OV64S            1'b0
`define OR1200_CPUCFGR_OV64S            1'b0
Line 1672... Line 1716...
`ifdef OR1200_NO_DC
`ifdef OR1200_NO_DC
`define OR1200_DCCFGR_NCW               3'h0    // Irrelevant
`define OR1200_DCCFGR_NCW               3'h0    // Irrelevant
`define OR1200_DCCFGR_NCS               4'h0    // Irrelevant
`define OR1200_DCCFGR_NCS               4'h0    // Irrelevant
`define OR1200_DCCFGR_CBS               1'b0    // Irrelevant
`define OR1200_DCCFGR_CBS               1'b0    // Irrelevant
`define OR1200_DCCFGR_CWS               1'b0    // Irrelevant
`define OR1200_DCCFGR_CWS               1'b0    // Irrelevant
`define OR1200_DCCFGR_CCRI              1'b1    // Irrelevant
`define OR1200_DCCFGR_CCRI              1'b0    // Irrelevant
`define OR1200_DCCFGR_CBIRI             1'b1    // Irrelevant
`define OR1200_DCCFGR_CBIRI             1'b0    // Irrelevant
`define OR1200_DCCFGR_CBPRI             1'b0    // Irrelevant
`define OR1200_DCCFGR_CBPRI             1'b0    // Irrelevant
`define OR1200_DCCFGR_CBLRI             1'b0    // Irrelevant
`define OR1200_DCCFGR_CBLRI             1'b0    // Irrelevant
`define OR1200_DCCFGR_CBFRI             1'b1    // Irrelevant
`define OR1200_DCCFGR_CBFRI             1'b0    // Irrelevant
`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
`define OR1200_DCCFGR_RES1              17'h00000
`define OR1200_DCCFGR_RES1              17'h00000
`else
`else
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
Line 1734... Line 1778...
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
`define OR1200_ICCFGR_RES1              17'h00000
`define OR1200_ICCFGR_RES1              17'h00000
`endif
`endif
 
 
// DCFGR fields
// DCFGR fields
`define OR1200_DCFGR_NDP_BITS           2:0
`define OR1200_DCFGR_NDP_BITS           3:0
`define OR1200_DCFGR_WPCI_BITS          3
`define OR1200_DCFGR_WPCI_BITS          4
`define OR1200_DCFGR_RES1_BITS          31:4
`define OR1200_DCFGR_RES1_BITS          31:5
 
 
// DCFGR values
// DCFGR values
`ifdef OR1200_DU_HWBKPTS
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DCFGR_NDP        3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
`define OR1200_DCFGR_NDP                4'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
`ifdef OR1200_DU_DWCR0
`ifdef OR1200_DU_DWCR0
`define OR1200_DCFGR_WPCI               1'b1
`define OR1200_DCFGR_WPCI               1'b1
`else
`else
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
`endif
`endif
`else
`else
`define OR1200_DCFGR_NDP                3'h0    // Zero DVR/DCR pairs
`define OR1200_DCFGR_NDP                4'h0    // Zero DVR/DCR pairs
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
`endif
`endif
`define OR1200_DCFGR_RES1               28'h0000000
`define OR1200_DCFGR_RES1               28'h0000000
 
 
 No newline at end of file
 No newline at end of file
 
///////////////////////////////////////////////////////////////////////////////
 
// Boot Address Selection                                                    //
 
///////////////////////////////////////////////////////////////////////////////
 
 // Boot from ROM at 0xf0000100
 
`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
 
`define OR1200_BOOT_ADR 32'hf0000100
 
// Boot from 0x100
 
// `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
 
// `define OR1200_BOOT_ADR 32'h00000100
 
 
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