| Line 1... |
Line 1... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's definitions ////
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//// OR1200's definitions ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Parameters of the OR1200 core ////
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//// Defines for the OR1200 core ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - add parameters that are missing ////
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//// - add parameters that are missing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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| Line 39... |
Line 39... |
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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//
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// $Log: or1200_defines.v,v $
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// $Log: or1200_defines.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Minor update:
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// Defines added, bugs fixed.
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// Defines added, bugs fixed.
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//
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// Revision 1.45 2006/04/09 01:32:29 lampret
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// See OR1200_MAC_SHIFTBY in or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts.
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//
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// Revision 1.44 2005/10/19 11:37:56 jcastillo
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// Added support for RAMB16 Xilinx4/Spartan3 primitives
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//
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// Revision 1.43 2005/01/07 09:23:39 andreje
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// l.ff1 and l.cmov instructions added
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//
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// Revision 1.42 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.41 2004/05/09 20:03:20 lampret
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// By default l.cust5 insns are disabled
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//
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// Revision 1.40 2004/05/09 19:49:04 lampret
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// Added some l.cust5 custom instructions as example
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//
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// Revision 1.39 2004/04/08 11:00:46 simont
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// Add support for 512B instruction cache.
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//
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// Revision 1.38 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.35.4.6 2004/02/11 01:40:11 lampret
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// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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//
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// Revision 1.35.4.5 2004/01/15 06:46:38 markom
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// interface to debug changed; no more opselect; stb-ack protocol
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//
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// Revision 1.35.4.4 2004/01/11 22:45:46 andreje
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// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
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//
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// Revision 1.35.4.3 2003/12/17 13:43:38 simons
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// Exception prefix configuration changed.
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//
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// Revision 1.35.4.2 2003/12/05 00:05:03 lampret
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// Static exception prefix.
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//
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// Revision 1.35.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.35 2003/04/24 00:16:07 lampret
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// No functional changes. Added defines to disable implementation of multiplier/MAC
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//
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// Revision 1.34 2003/04/20 22:23:57 lampret
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// No functional change. Only added customization for exception vectors.
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//
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// Revision 1.33 2003/04/07 20:56:07 lampret
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// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
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//
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// Revision 1.32 2003/04/07 01:26:57 lampret
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// RFRAM defines comments updated. Altera LPM option added.
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//
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// Revision 1.31 2002/12/08 08:57:56 lampret
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// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
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//
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// Revision 1.30 2002/10/28 15:09:22 mohor
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// Previous check-in was done by mistake.
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//
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// Revision 1.29 2002/10/28 15:03:50 mohor
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// Signal scanb_sen renamed to scanb_en.
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//
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// Revision 1.28 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.27 2002/09/16 03:13:23 lampret
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// Removed obsolete comment.
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//
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// Revision 1.26 2002/09/08 05:52:16 lampret
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// Added optional l.div/l.divu insns. By default they are disabled.
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//
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// Revision 1.25 2002/09/07 19:16:10 lampret
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// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
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//
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// Revision 1.24 2002/09/07 05:42:02 lampret
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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//
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// Revision 1.23 2002/09/04 00:50:34 lampret
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// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
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//
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// Revision 1.22 2002/09/03 22:28:21 lampret
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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//
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// Revision 1.21 2002/08/22 02:18:55 lampret
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// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
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//
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// Revision 1.20 2002/08/18 21:59:45 lampret
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// Disable SB until it is tested
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//
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// Revision 1.19 2002/08/18 19:53:08 lampret
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// Added store buffer.
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//
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// Revision 1.18 2002/08/15 06:04:11 lampret
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// Fixed Xilinx trace buffer address. REported by Taylor Su.
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//
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// Revision 1.17 2002/08/12 05:31:44 lampret
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// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
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//
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// Revision 1.16 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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// Revision 1.15 2002/06/08 16:20:21 lampret
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// Added defines for enabling generic FF based memory macro for register file.
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//
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// Revision 1.14 2002/03/29 16:24:06 lampret
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// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives
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//
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// Revision 1.13 2002/03/29 15:16:55 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.12 2002/03/28 19:25:42 lampret
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// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
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//
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// Revision 1.11 2002/03/28 19:13:17 lampret
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// Updated defines.
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//
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// Revision 1.10 2002/03/14 00:30:24 lampret
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// Added alternative for critical path in DU.
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//
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// Revision 1.9 2002/03/11 01:26:26 lampret
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// Fixed async loop. Changed multiplier type for ASIC.
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//
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// Revision 1.8 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.7 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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//
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// Revision 1.6 2002/01/19 14:10:22 lampret
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// Fixed OR1200_XILINX_RAM32X1D.
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//
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// Revision 1.5 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.4 2002/01/14 09:44:12 lampret
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// Default ASIC configuration does not sample WB inputs.
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//
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// Revision 1.3 2002/01/08 00:51:08 lampret
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// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
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//
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// Revision 1.2 2002/01/03 21:23:03 lampret
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// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.20 2001/12/04 05:02:36 lampret
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// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
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//
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// Revision 1.19 2001/11/27 19:46:57 lampret
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// Now FPGA and ASIC target are separate.
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//
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// Revision 1.18 2001/11/23 21:42:31 simons
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// Program counter divided to PPC and NPC.
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//
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// Revision 1.17 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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//
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// Revision 1.16 2001/11/20 21:30:38 lampret
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// Added OR1200_REGISTERED_INPUTS.
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//
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// Revision 1.15 2001/11/19 14:29:48 simons
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// Cashes disabled.
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//
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// Revision 1.14 2001/11/13 10:02:21 lampret
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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//
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// Revision 1.13 2001/11/12 01:45:40 lampret
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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//
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// Revision 1.12 2001/11/10 03:43:57 lampret
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// Fixed exceptions.
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//
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// Revision 1.11 2001/11/02 18:57:14 lampret
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// Modified virtual silicon instantiations.
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//
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.9 2001/10/19 23:28:46 lampret
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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//
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// Revision 1.8 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.3 2001/08/17 08:01:19 lampret
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// IC enable/disable.
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//
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// Revision 1.2 2001/08/13 03:36:20 lampret
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
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// Revision 1.1 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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// Dump VCD
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// Dump VCD
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//
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//
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//`define OR1200_VCD_DUMP
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//`define OR1200_VCD_DUMP
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| Line 582... |
Line 374... |
// in execution is not multiply instruction
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// in execution is not multiply instruction
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//
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//
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//`define OR1200_LOWPWR_MULT
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//`define OR1200_LOWPWR_MULT
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//
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//
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// Implement HW Single Precision FPU
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//
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//`define OR1200_FPU_IMPLEMENTED
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|
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//
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// Clock ratio RISC clock versus WB clock
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// Clock ratio RISC clock versus WB clock
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//
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//
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// If you plan to run WB:RISC clock fixed to 1:1, disable
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// If you plan to run WB:RISC clock fixed to 1:1, disable
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// both defines
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// both defines
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//
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//
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| Line 668... |
Line 465... |
`define OR1200_SHROTOP_SRL 2'd1
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`define OR1200_SHROTOP_SRL 2'd1
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`define OR1200_SHROTOP_SRA 2'd2
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`define OR1200_SHROTOP_SRA 2'd2
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`define OR1200_SHROTOP_ROR 2'd3
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`define OR1200_SHROTOP_ROR 2'd3
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|
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// Execution cycles per instruction
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// Execution cycles per instruction
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`define OR1200_MULTICYCLE_WIDTH 2
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`define OR1200_MULTICYCLE_WIDTH 3
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`define OR1200_ONE_CYCLE 2'd0
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`define OR1200_ONE_CYCLE 3'd0
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`define OR1200_TWO_CYCLES 2'd1
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`define OR1200_TWO_CYCLES 3'd1
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|
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// Operand MUX selects
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// Operand MUX selects
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`define OR1200_SEL_WIDTH 2
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`define OR1200_SEL_WIDTH 2
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`define OR1200_SEL_RF 2'd0
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`define OR1200_SEL_RF 2'd0
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`define OR1200_SEL_IMM 2'd1
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`define OR1200_SEL_IMM 2'd1
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| Line 726... |
Line 523... |
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//
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//
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// Register File Write-Back OPs
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// Register File Write-Back OPs
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//
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//
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// Bit 0: register file write enable
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// Bit 0: register file write enable
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// Bits 2-1: write-back mux selects
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// Bits 3-1: write-back mux selects
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`define OR1200_RFWBOP_WIDTH 3
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//
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`define OR1200_RFWBOP_NOP 3'b000
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`define OR1200_RFWBOP_WIDTH 4
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`define OR1200_RFWBOP_ALU 3'b001
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`define OR1200_RFWBOP_NOP 4'b0000
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`define OR1200_RFWBOP_LSU 3'b011
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`define OR1200_RFWBOP_ALU 3'b000
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`define OR1200_RFWBOP_SPRS 3'b101
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`define OR1200_RFWBOP_LSU 3'b001
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`define OR1200_RFWBOP_LR 3'b111
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`define OR1200_RFWBOP_SPRS 3'b010
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`define OR1200_RFWBOP_LR 3'b011
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`define OR1200_RFWBOP_FPU 3'b100
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|
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// Compare instructions
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// Compare instructions
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`define OR1200_COP_SFEQ 3'b000
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`define OR1200_COP_SFEQ 3'b000
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`define OR1200_COP_SFNE 3'b001
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`define OR1200_COP_SFNE 3'b001
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`define OR1200_COP_SFGT 3'b010
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`define OR1200_COP_SFGT 3'b010
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| Line 746... |
Line 545... |
`define OR1200_COP_X 3'b111
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`define OR1200_COP_X 3'b111
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`define OR1200_SIGNED_COMPARE 'd3
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`define OR1200_SIGNED_COMPARE 'd3
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`define OR1200_COMPOP_WIDTH 4
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`define OR1200_COMPOP_WIDTH 4
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|
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//
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//
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// FP OPs
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//
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// MSbit indicates FPU operation valid
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//
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`define OR1200_FPUOP_WIDTH 8
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// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles
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`define OR1200_FPUOP_CYCLES 3'd4
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// FP instruction is double precision if bit 4 is set. We're a 32-bit
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// implementation thus do not support double precision FP
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`define OR1200_FPUOP_DOUBLE_BIT 4
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`define OR1200_FPUOP_ADD 8'b0000_0000
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`define OR1200_FPUOP_SUB 8'b0000_0001
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`define OR1200_FPUOP_MUL 8'b0000_0010
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`define OR1200_FPUOP_DIV 8'b0000_0011
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`define OR1200_FPUOP_ITOF 8'b0000_0100
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`define OR1200_FPUOP_FTOI 8'b0000_0101
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`define OR1200_FPUOP_REM 8'b0000_0110
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`define OR1200_FPUOP_RESERVED 8'b0000_0111
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// FP Compare instructions
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`define OR1200_FPCOP_SFEQ 8'b0000_1000
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`define OR1200_FPCOP_SFNE 8'b0000_1001
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`define OR1200_FPCOP_SFGT 8'b0000_1010
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`define OR1200_FPCOP_SFGE 8'b0000_1011
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`define OR1200_FPCOP_SFLT 8'b0000_1100
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`define OR1200_FPCOP_SFLE 8'b0000_1101
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|
|
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//
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// TAGs for instruction bus
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// TAGs for instruction bus
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//
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//
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`define OR1200_ITAG_IDLE 4'h0 // idle bus
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`define OR1200_ITAG_IDLE 4'h0 // idle bus
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`define OR1200_ITAG_NI 4'h1 // normal insn
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`define OR1200_ITAG_NI 4'h1 // normal insn
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`define OR1200_ITAG_BE 4'hb // Bus error exception
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`define OR1200_ITAG_BE 4'hb // Bus error exception
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| Line 809... |
Line 635... |
`define OR1200_OR32_SH_ROTI 6'b101110
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`define OR1200_OR32_SH_ROTI 6'b101110
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`define OR1200_OR32_SFXXI 6'b101111
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`define OR1200_OR32_SFXXI 6'b101111
|
/* */
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/* */
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`define OR1200_OR32_MTSPR 6'b110000
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`define OR1200_OR32_MTSPR 6'b110000
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`define OR1200_OR32_MACMSB 6'b110001
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`define OR1200_OR32_MACMSB 6'b110001
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|
`define OR1200_OR32_FLOAT 6'b110010
|
/* */
|
/* */
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`define OR1200_OR32_SW 6'b110101
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`define OR1200_OR32_SW 6'b110101
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`define OR1200_OR32_SB 6'b110110
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`define OR1200_OR32_SB 6'b110110
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`define OR1200_OR32_SH 6'b110111
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`define OR1200_OR32_SH 6'b110111
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`define OR1200_OR32_ALU 6'b111000
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`define OR1200_OR32_ALU 6'b111000
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| Line 862... |
Line 689... |
// To avoid implementation of a certain exception,
|
// To avoid implementation of a certain exception,
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// simply comment out corresponding line
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// simply comment out corresponding line
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//
|
//
|
`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf
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`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf
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`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he
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`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he
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`define OR1200_EXCEPT_BREAK `OR1200_EXCEPT_WIDTH'hd
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`define OR1200_EXCEPT_FLOAT `OR1200_EXCEPT_WIDTH'hd
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`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc
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`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc
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`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb
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`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb
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`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha
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`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha
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`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9
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`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9
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`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8
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`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8
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| Line 903... |
Line 730... |
`define OR1200_SPR_GROUP_MAC 5'd05
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`define OR1200_SPR_GROUP_MAC 5'd05
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`define OR1200_SPR_GROUP_DU 5'd06
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`define OR1200_SPR_GROUP_DU 5'd06
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`define OR1200_SPR_GROUP_PM 5'd08
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`define OR1200_SPR_GROUP_PM 5'd08
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`define OR1200_SPR_GROUP_PIC 5'd09
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`define OR1200_SPR_GROUP_PIC 5'd09
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`define OR1200_SPR_GROUP_TT 5'd10
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`define OR1200_SPR_GROUP_TT 5'd10
|
|
`define OR1200_SPR_GROUP_FPU 5'd11
|
|
|
/////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////
|
//
|
//
|
// System group
|
// System group
|
//
|
//
|
| Line 918... |
Line 745... |
`define OR1200_SPR_CFGR 7'd0
|
`define OR1200_SPR_CFGR 7'd0
|
`define OR1200_SPR_RF 6'd32 // 1024 >> 5
|
`define OR1200_SPR_RF 6'd32 // 1024 >> 5
|
`define OR1200_SPR_NPC 11'd16
|
`define OR1200_SPR_NPC 11'd16
|
`define OR1200_SPR_SR 11'd17
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`define OR1200_SPR_SR 11'd17
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`define OR1200_SPR_PPC 11'd18
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`define OR1200_SPR_PPC 11'd18
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`define OR1200_SPR_FPCSR 11'd20
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`define OR1200_SPR_EPCR 11'd32
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`define OR1200_SPR_EPCR 11'd32
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`define OR1200_SPR_EEAR 11'd48
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`define OR1200_SPR_EEAR 11'd48
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`define OR1200_SPR_ESR 11'd64
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`define OR1200_SPR_ESR 11'd64
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//
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//
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| Line 958... |
Line 786... |
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
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// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
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// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
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// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
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//
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//
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`define OR1200_SR_EPH_DEF 1'b0
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`define OR1200_SR_EPH_DEF 1'b0
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//
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// FPCSR bits
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//
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`define OR1200_FPCSR_WIDTH 12
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`define OR1200_FPCSR_FPEE 0
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`define OR1200_FPCSR_RM 2:1
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`define OR1200_FPCSR_OVF 3
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`define OR1200_FPCSR_UNF 4
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`define OR1200_FPCSR_SNF 5
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`define OR1200_FPCSR_QNF 6
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`define OR1200_FPCSR_ZF 7
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`define OR1200_FPCSR_IXF 8
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`define OR1200_FPCSR_IVF 9
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`define OR1200_FPCSR_INF 10
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`define OR1200_FPCSR_DZF 11
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`define OR1200_FPCSR_RES 31:12
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/////////////////////////////////////////////////////
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/////////////////////////////////////////////////////
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//
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//
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// Power Management (PM)
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// Power Management (PM)
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//
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//
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| Line 1106... |
Line 952... |
`define OR1200_DU_DSR_IE 7
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`define OR1200_DU_DSR_IE 7
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`define OR1200_DU_DSR_DME 8
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`define OR1200_DU_DSR_DME 8
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`define OR1200_DU_DSR_IME 9
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`define OR1200_DU_DSR_IME 9
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`define OR1200_DU_DSR_RE 10
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`define OR1200_DU_DSR_RE 10
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`define OR1200_DU_DSR_SCE 11
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`define OR1200_DU_DSR_SCE 11
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`define OR1200_DU_DSR_BE 12
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`define OR1200_DU_DSR_FPE 12
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`define OR1200_DU_DSR_TE 13
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`define OR1200_DU_DSR_TE 13
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// DRR bits
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// DRR bits
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`define OR1200_DU_DRR_RSTE 0
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`define OR1200_DU_DRR_RSTE 0
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`define OR1200_DU_DRR_BUSEE 1
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`define OR1200_DU_DRR_BUSEE 1
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| Line 1122... |
Line 968... |
`define OR1200_DU_DRR_IE 7
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`define OR1200_DU_DRR_IE 7
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`define OR1200_DU_DRR_DME 8
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`define OR1200_DU_DRR_DME 8
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`define OR1200_DU_DRR_IME 9
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`define OR1200_DU_DRR_IME 9
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`define OR1200_DU_DRR_RE 10
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`define OR1200_DU_DRR_RE 10
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`define OR1200_DU_DRR_SCE 11
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`define OR1200_DU_DRR_SCE 11
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`define OR1200_DU_DRR_BE 12
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`define OR1200_DU_DRR_FPE 12
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`define OR1200_DU_DRR_TE 13
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`define OR1200_DU_DRR_TE 13
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// Define if reading DU regs is allowed
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// Define if reading DU regs is allowed
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`define OR1200_DU_READREGS
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`define OR1200_DU_READREGS
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| Line 1798... |
Line 1644... |
`endif
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`endif
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`define OR1200_DCFGR_RES1 28'h0000000
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`define OR1200_DCFGR_RES1 28'h0000000
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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// Boot Address Selection //
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// Boot Address Selection //
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// This only changes where the initial reset occurs. EPH setting is still //
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// used to determine where vectors are located. //
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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// Boot from ROM at 0xf0000100
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// Boot from 0xf0000100
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`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
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`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
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`define OR1200_BOOT_ADR 32'hf0000100
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`define OR1200_BOOT_ADR 32'hf0000100
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// Boot from 0x100
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// Boot from 0x100
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// `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
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// `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
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// `define OR1200_BOOT_ADR 32'h00000100
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// `define OR1200_BOOT_ADR 32'h00000100
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