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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  OR1200's definitions                                        ////
////  OR1200's definitions                                        ////
////                                                              ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////  http://opencores.org/project,or1k                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Parameters of the OR1200 core                               ////
////  Defines for the OR1200 core                                 ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add parameters that are missing                          ////
////   - add parameters that are missing                          ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
Line 39... Line 39...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
 
//
 
// $Log: or1200_defines.v,v $
// $Log: or1200_defines.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Minor update: 
// Defines added, bugs fixed. 
// Defines added, bugs fixed. 
//
 
// Revision 1.45  2006/04/09 01:32:29  lampret
 
// See OR1200_MAC_SHIFTBY in or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts.
 
//
 
// Revision 1.44  2005/10/19 11:37:56  jcastillo
 
// Added support for RAMB16 Xilinx4/Spartan3 primitives
 
//
 
// Revision 1.43  2005/01/07 09:23:39  andreje
 
// l.ff1 and l.cmov instructions added
 
//
 
// Revision 1.42  2004/06/08 18:17:36  lampret
 
// Non-functional changes. Coding style fixes.
 
//
 
// Revision 1.41  2004/05/09 20:03:20  lampret
 
// By default l.cust5 insns are disabled
 
//
 
// Revision 1.40  2004/05/09 19:49:04  lampret
 
// Added some l.cust5 custom instructions as example
 
//
 
// Revision 1.39  2004/04/08 11:00:46  simont
 
// Add support for 512B instruction cache.
 
//
 
// Revision 1.38  2004/04/05 08:29:57  lampret
 
// Merged branch_qmem into main tree.
 
//
 
// Revision 1.35.4.6  2004/02/11 01:40:11  lampret
 
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
 
//
 
// Revision 1.35.4.5  2004/01/15 06:46:38  markom
 
// interface to debug changed; no more opselect; stb-ack protocol
 
//
 
// Revision 1.35.4.4  2004/01/11 22:45:46  andreje
 
// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
 
//
 
// Revision 1.35.4.3  2003/12/17 13:43:38  simons
 
// Exception prefix configuration changed.
 
//
 
// Revision 1.35.4.2  2003/12/05 00:05:03  lampret
 
// Static exception prefix.
 
//
 
// Revision 1.35.4.1  2003/07/08 15:36:37  lampret
 
// Added embedded memory QMEM.
 
//
 
// Revision 1.35  2003/04/24 00:16:07  lampret
 
// No functional changes. Added defines to disable implementation of multiplier/MAC
 
//
 
// Revision 1.34  2003/04/20 22:23:57  lampret
 
// No functional change. Only added customization for exception vectors.
 
//
 
// Revision 1.33  2003/04/07 20:56:07  lampret
 
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
 
//
 
// Revision 1.32  2003/04/07 01:26:57  lampret
 
// RFRAM defines comments updated. Altera LPM option added.
 
//
 
// Revision 1.31  2002/12/08 08:57:56  lampret
 
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
 
//
 
// Revision 1.30  2002/10/28 15:09:22  mohor
 
// Previous check-in was done by mistake.
 
//
 
// Revision 1.29  2002/10/28 15:03:50  mohor
 
// Signal scanb_sen renamed to scanb_en.
 
//
 
// Revision 1.28  2002/10/17 20:04:40  lampret
 
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
 
//
 
// Revision 1.27  2002/09/16 03:13:23  lampret
 
// Removed obsolete comment.
 
//
 
// Revision 1.26  2002/09/08 05:52:16  lampret
 
// Added optional l.div/l.divu insns. By default they are disabled.
 
//
 
// Revision 1.25  2002/09/07 19:16:10  lampret
 
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
 
//
 
// Revision 1.24  2002/09/07 05:42:02  lampret
 
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
 
//
 
// Revision 1.23  2002/09/04 00:50:34  lampret
 
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
 
//
 
// Revision 1.22  2002/09/03 22:28:21  lampret
 
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
 
//
 
// Revision 1.21  2002/08/22 02:18:55  lampret
 
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
 
//
 
// Revision 1.20  2002/08/18 21:59:45  lampret
 
// Disable SB until it is tested
 
//
 
// Revision 1.19  2002/08/18 19:53:08  lampret
 
// Added store buffer.
 
//
 
// Revision 1.18  2002/08/15 06:04:11  lampret
 
// Fixed Xilinx trace buffer address. REported by Taylor Su.
 
//
 
// Revision 1.17  2002/08/12 05:31:44  lampret
 
// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
 
//
 
// Revision 1.16  2002/07/14 22:17:17  lampret
 
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
 
//
 
// Revision 1.15  2002/06/08 16:20:21  lampret
 
// Added defines for enabling generic FF based memory macro for register file.
 
//
 
// Revision 1.14  2002/03/29 16:24:06  lampret
 
// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives
 
//
 
// Revision 1.13  2002/03/29 15:16:55  lampret
 
// Some of the warnings fixed.
 
//
 
// Revision 1.12  2002/03/28 19:25:42  lampret
 
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
 
//
 
// Revision 1.11  2002/03/28 19:13:17  lampret
 
// Updated defines.
 
//
 
// Revision 1.10  2002/03/14 00:30:24  lampret
 
// Added alternative for critical path in DU.
 
//
 
// Revision 1.9  2002/03/11 01:26:26  lampret
 
// Fixed async loop. Changed multiplier type for ASIC.
 
//
 
// Revision 1.8  2002/02/11 04:33:17  lampret
 
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
 
//
 
// Revision 1.7  2002/02/01 19:56:54  lampret
 
// Fixed combinational loops.
 
//
 
// Revision 1.6  2002/01/19 14:10:22  lampret
 
// Fixed OR1200_XILINX_RAM32X1D.
 
//
 
// Revision 1.5  2002/01/18 07:56:00  lampret
 
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
 
//
 
// Revision 1.4  2002/01/14 09:44:12  lampret
 
// Default ASIC configuration does not sample WB inputs.
 
//
 
// Revision 1.3  2002/01/08 00:51:08  lampret
 
// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
 
//
 
// Revision 1.2  2002/01/03 21:23:03  lampret
 
// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.
 
//
 
// Revision 1.1  2002/01/03 08:16:15  lampret
 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
 
//
 
// Revision 1.20  2001/12/04 05:02:36  lampret
 
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
 
//
 
// Revision 1.19  2001/11/27 19:46:57  lampret
 
// Now FPGA and ASIC target are separate.
 
//
 
// Revision 1.18  2001/11/23 21:42:31  simons
 
// Program counter divided to PPC and NPC.
 
//
 
// Revision 1.17  2001/11/23 08:38:51  lampret
 
// Changed DSR/DRR behavior and exception detection.
 
//
 
// Revision 1.16  2001/11/20 21:30:38  lampret
 
// Added OR1200_REGISTERED_INPUTS.
 
//
 
// Revision 1.15  2001/11/19 14:29:48  simons
 
// Cashes disabled.
 
//
 
// Revision 1.14  2001/11/13 10:02:21  lampret
 
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
 
//
 
// Revision 1.13  2001/11/12 01:45:40  lampret
 
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
 
//
 
// Revision 1.12  2001/11/10 03:43:57  lampret
 
// Fixed exceptions.
 
//
 
// Revision 1.11  2001/11/02 18:57:14  lampret
 
// Modified virtual silicon instantiations.
 
//
 
// Revision 1.10  2001/10/21 17:57:16  lampret
 
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
 
//
 
// Revision 1.9  2001/10/19 23:28:46  lampret
 
// Fixed some synthesis warnings. Configured with caches and MMUs.
 
//
 
// Revision 1.8  2001/10/14 13:12:09  lampret
 
// MP3 version.
 
//
 
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
 
// no message
 
//
 
// Revision 1.3  2001/08/17 08:01:19  lampret
 
// IC enable/disable.
 
//
 
// Revision 1.2  2001/08/13 03:36:20  lampret
 
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
 
//
 
// Revision 1.1  2001/08/09 13:39:33  lampret
 
// Major clean-up.
 
//
 
// Revision 1.2  2001/07/22 03:31:54  lampret
 
// Fixed RAM's oen bug. Cache bypass under development.
 
//
 
// Revision 1.1  2001/07/20 00:46:03  lampret
 
// Development version of RTL. Libraries are missing.
 
//
 
//
 
 
 
//
//
// Dump VCD
// Dump VCD
//
//
//`define OR1200_VCD_DUMP
//`define OR1200_VCD_DUMP
Line 582... Line 374...
// in execution is not multiply instruction
// in execution is not multiply instruction
//
//
//`define OR1200_LOWPWR_MULT
//`define OR1200_LOWPWR_MULT
 
 
//
//
 
// Implement HW Single Precision FPU
 
//
 
//`define OR1200_FPU_IMPLEMENTED
 
 
 
//
// Clock ratio RISC clock versus WB clock
// Clock ratio RISC clock versus WB clock
//
//
// If you plan to run WB:RISC clock fixed to 1:1, disable
// If you plan to run WB:RISC clock fixed to 1:1, disable
// both defines
// both defines
//
//
Line 668... Line 465...
`define OR1200_SHROTOP_SRL      2'd1
`define OR1200_SHROTOP_SRL      2'd1
`define OR1200_SHROTOP_SRA      2'd2
`define OR1200_SHROTOP_SRA      2'd2
`define OR1200_SHROTOP_ROR      2'd3
`define OR1200_SHROTOP_ROR      2'd3
 
 
// Execution cycles per instruction
// Execution cycles per instruction
`define OR1200_MULTICYCLE_WIDTH 2
`define OR1200_MULTICYCLE_WIDTH 3
`define OR1200_ONE_CYCLE                2'd0
`define OR1200_ONE_CYCLE                3'd0
`define OR1200_TWO_CYCLES               2'd1
`define OR1200_TWO_CYCLES               3'd1
 
 
// Operand MUX selects
// Operand MUX selects
`define OR1200_SEL_WIDTH                2
`define OR1200_SEL_WIDTH                2
`define OR1200_SEL_RF                   2'd0
`define OR1200_SEL_RF                   2'd0
`define OR1200_SEL_IMM                  2'd1
`define OR1200_SEL_IMM                  2'd1
Line 726... Line 523...
 
 
//
//
// Register File Write-Back OPs
// Register File Write-Back OPs
//
//
// Bit 0: register file write enable
// Bit 0: register file write enable
// Bits 2-1: write-back mux selects
// Bits 3-1: write-back mux selects
`define OR1200_RFWBOP_WIDTH             3
//
`define OR1200_RFWBOP_NOP               3'b000
 `define OR1200_RFWBOP_WIDTH            4
`define OR1200_RFWBOP_ALU               3'b001
 `define OR1200_RFWBOP_NOP              4'b0000
`define OR1200_RFWBOP_LSU               3'b011
 `define OR1200_RFWBOP_ALU              3'b000
`define OR1200_RFWBOP_SPRS              3'b101
 `define OR1200_RFWBOP_LSU              3'b001
`define OR1200_RFWBOP_LR                3'b111
 `define OR1200_RFWBOP_SPRS             3'b010
 
 `define OR1200_RFWBOP_LR               3'b011
 
 `define OR1200_RFWBOP_FPU              3'b100
 
 
// Compare instructions
// Compare instructions
`define OR1200_COP_SFEQ       3'b000
`define OR1200_COP_SFEQ       3'b000
`define OR1200_COP_SFNE       3'b001
`define OR1200_COP_SFNE       3'b001
`define OR1200_COP_SFGT       3'b010
`define OR1200_COP_SFGT       3'b010
Line 746... Line 545...
`define OR1200_COP_X          3'b111
`define OR1200_COP_X          3'b111
`define OR1200_SIGNED_COMPARE 'd3
`define OR1200_SIGNED_COMPARE 'd3
`define OR1200_COMPOP_WIDTH     4
`define OR1200_COMPOP_WIDTH     4
 
 
//
//
 
// FP OPs
 
//
 
// MSbit indicates FPU operation valid
 
//
 
`define OR1200_FPUOP_WIDTH      8
 
// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles
 
`define OR1200_FPUOP_CYCLES 3'd4
 
// FP instruction is double precision if bit 4 is set. We're a 32-bit 
 
// implementation thus do not support double precision FP 
 
`define OR1200_FPUOP_DOUBLE_BIT 4
 
`define OR1200_FPUOP_ADD  8'b0000_0000
 
`define OR1200_FPUOP_SUB  8'b0000_0001
 
`define OR1200_FPUOP_MUL  8'b0000_0010
 
`define OR1200_FPUOP_DIV  8'b0000_0011
 
`define OR1200_FPUOP_ITOF 8'b0000_0100
 
`define OR1200_FPUOP_FTOI 8'b0000_0101
 
`define OR1200_FPUOP_REM  8'b0000_0110
 
`define OR1200_FPUOP_RESERVED  8'b0000_0111
 
// FP Compare instructions
 
`define OR1200_FPCOP_SFEQ 8'b0000_1000
 
`define OR1200_FPCOP_SFNE 8'b0000_1001
 
`define OR1200_FPCOP_SFGT 8'b0000_1010
 
`define OR1200_FPCOP_SFGE 8'b0000_1011
 
`define OR1200_FPCOP_SFLT 8'b0000_1100
 
`define OR1200_FPCOP_SFLE 8'b0000_1101
 
 
 
//
// TAGs for instruction bus
// TAGs for instruction bus
//
//
`define OR1200_ITAG_IDLE        4'h0    // idle bus
`define OR1200_ITAG_IDLE        4'h0    // idle bus
`define OR1200_ITAG_NI          4'h1    // normal insn
`define OR1200_ITAG_NI          4'h1    // normal insn
`define OR1200_ITAG_BE          4'hb    // Bus error exception
`define OR1200_ITAG_BE          4'hb    // Bus error exception
Line 809... Line 635...
`define OR1200_OR32_SH_ROTI           6'b101110
`define OR1200_OR32_SH_ROTI           6'b101110
`define OR1200_OR32_SFXXI             6'b101111
`define OR1200_OR32_SFXXI             6'b101111
/* */
/* */
`define OR1200_OR32_MTSPR             6'b110000
`define OR1200_OR32_MTSPR             6'b110000
`define OR1200_OR32_MACMSB            6'b110001
`define OR1200_OR32_MACMSB            6'b110001
 
`define OR1200_OR32_FLOAT             6'b110010
/* */
/* */
`define OR1200_OR32_SW                6'b110101
`define OR1200_OR32_SW                6'b110101
`define OR1200_OR32_SB                6'b110110
`define OR1200_OR32_SB                6'b110110
`define OR1200_OR32_SH                6'b110111
`define OR1200_OR32_SH                6'b110111
`define OR1200_OR32_ALU               6'b111000
`define OR1200_OR32_ALU               6'b111000
Line 862... Line 689...
// To avoid implementation of a certain exception,
// To avoid implementation of a certain exception,
// simply comment out corresponding line
// simply comment out corresponding line
//
//
`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf
`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf
`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he
`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he
`define OR1200_EXCEPT_BREAK             `OR1200_EXCEPT_WIDTH'hd
`define OR1200_EXCEPT_FLOAT             `OR1200_EXCEPT_WIDTH'hd
`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc
`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc
`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb
`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb
`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha
`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha
`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9
`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9
`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8
`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8
Line 903... Line 730...
`define OR1200_SPR_GROUP_MAC    5'd05
`define OR1200_SPR_GROUP_MAC    5'd05
`define OR1200_SPR_GROUP_DU     5'd06
`define OR1200_SPR_GROUP_DU     5'd06
`define OR1200_SPR_GROUP_PM     5'd08
`define OR1200_SPR_GROUP_PM     5'd08
`define OR1200_SPR_GROUP_PIC    5'd09
`define OR1200_SPR_GROUP_PIC    5'd09
`define OR1200_SPR_GROUP_TT     5'd10
`define OR1200_SPR_GROUP_TT     5'd10
 
`define OR1200_SPR_GROUP_FPU    5'd11
 
 
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
//
//
// System group
// System group
//
//
Line 918... Line 745...
`define OR1200_SPR_CFGR         7'd0
`define OR1200_SPR_CFGR         7'd0
`define OR1200_SPR_RF           6'd32   // 1024 >> 5
`define OR1200_SPR_RF           6'd32   // 1024 >> 5
`define OR1200_SPR_NPC          11'd16
`define OR1200_SPR_NPC          11'd16
`define OR1200_SPR_SR           11'd17
`define OR1200_SPR_SR           11'd17
`define OR1200_SPR_PPC          11'd18
`define OR1200_SPR_PPC          11'd18
 
`define OR1200_SPR_FPCSR        11'd20
`define OR1200_SPR_EPCR         11'd32
`define OR1200_SPR_EPCR         11'd32
`define OR1200_SPR_EEAR         11'd48
`define OR1200_SPR_EEAR         11'd48
`define OR1200_SPR_ESR          11'd64
`define OR1200_SPR_ESR          11'd64
 
 
//
//
Line 958... Line 786...
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
//
//
`define OR1200_SR_EPH_DEF       1'b0
`define OR1200_SR_EPH_DEF       1'b0
 
 
 
 
 
//
 
// FPCSR bits
 
//
 
`define OR1200_FPCSR_WIDTH 12
 
`define OR1200_FPCSR_FPEE  0
 
`define OR1200_FPCSR_RM    2:1
 
`define OR1200_FPCSR_OVF   3
 
`define OR1200_FPCSR_UNF   4
 
`define OR1200_FPCSR_SNF   5
 
`define OR1200_FPCSR_QNF   6
 
`define OR1200_FPCSR_ZF    7
 
`define OR1200_FPCSR_IXF   8
 
`define OR1200_FPCSR_IVF   9
 
`define OR1200_FPCSR_INF   10
 
`define OR1200_FPCSR_DZF   11
 
`define OR1200_FPCSR_RES   31:12
 
 
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
//
//
// Power Management (PM)
// Power Management (PM)
//
//
 
 
Line 1106... Line 952...
`define OR1200_DU_DSR_IE        7
`define OR1200_DU_DSR_IE        7
`define OR1200_DU_DSR_DME       8
`define OR1200_DU_DSR_DME       8
`define OR1200_DU_DSR_IME       9
`define OR1200_DU_DSR_IME       9
`define OR1200_DU_DSR_RE        10
`define OR1200_DU_DSR_RE        10
`define OR1200_DU_DSR_SCE       11
`define OR1200_DU_DSR_SCE       11
`define OR1200_DU_DSR_BE        12
`define OR1200_DU_DSR_FPE       12
`define OR1200_DU_DSR_TE        13
`define OR1200_DU_DSR_TE        13
 
 
// DRR bits
// DRR bits
`define OR1200_DU_DRR_RSTE      0
`define OR1200_DU_DRR_RSTE      0
`define OR1200_DU_DRR_BUSEE     1
`define OR1200_DU_DRR_BUSEE     1
Line 1122... Line 968...
`define OR1200_DU_DRR_IE        7
`define OR1200_DU_DRR_IE        7
`define OR1200_DU_DRR_DME       8
`define OR1200_DU_DRR_DME       8
`define OR1200_DU_DRR_IME       9
`define OR1200_DU_DRR_IME       9
`define OR1200_DU_DRR_RE        10
`define OR1200_DU_DRR_RE        10
`define OR1200_DU_DRR_SCE       11
`define OR1200_DU_DRR_SCE       11
`define OR1200_DU_DRR_BE        12
`define OR1200_DU_DRR_FPE       12
`define OR1200_DU_DRR_TE        13
`define OR1200_DU_DRR_TE        13
 
 
// Define if reading DU regs is allowed
// Define if reading DU regs is allowed
`define OR1200_DU_READREGS
`define OR1200_DU_READREGS
 
 
Line 1798... Line 1644...
`endif
`endif
`define OR1200_DCFGR_RES1               28'h0000000
`define OR1200_DCFGR_RES1               28'h0000000
 
 
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// Boot Address Selection                                                    //
// Boot Address Selection                                                    //
 
// This only changes where the initial reset occurs. EPH setting is still    //
 
// used to determine where vectors are located.                              //
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
 // Boot from ROM at 0xf0000100
 // Boot from 0xf0000100
`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
`define OR1200_BOOT_ADR 32'hf0000100
`define OR1200_BOOT_ADR 32'hf0000100
// Boot from 0x100
// Boot from 0x100
// `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
// `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
// `define OR1200_BOOT_ADR 32'h00000100
// `define OR1200_BOOT_ADR 32'h00000100

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