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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 258 and 259

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Rev 258 Rev 259
Line 380... Line 380...
//
//
// Implement HW Single Precision FPU
// Implement HW Single Precision FPU
//
//
//`define OR1200_FPU_IMPLEMENTED
//`define OR1200_FPU_IMPLEMENTED
//
//
// Select modules for FPU
 
`ifdef OR1200_FPU_IMPLEMENTED
 
// FPU arithmetic module (add,sub,mul,div)
 
 `define OR1200_FPU_ARITH_FPU100
 
// FPU conversion module (int-float,float-int)
 
 `define OR1200_FPU_CONV_USSELMANN
 
// FPU comparison module
 
 `define OR1200_FPU_COMP_USSELMANN
 
`endif
 
 
 
//
//
// Clock ratio RISC clock versus WB clock
// Clock ratio RISC clock versus WB clock
//
//
// If you plan to run WB:RISC clock fixed to 1:1, disable
// If you plan to run WB:RISC clock fixed to 1:1, disable

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