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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 358 and 364

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Line 920... Line 920...
`endif
`endif
`define OR1200_DU_DSR           11'd20
`define OR1200_DU_DSR           11'd20
`define OR1200_DU_DRR           11'd21
`define OR1200_DU_DRR           11'd21
`ifdef OR1200_DU_TB_IMPLEMENTED
`ifdef OR1200_DU_TB_IMPLEMENTED
`define OR1200_DU_TBADR         11'h0ff
`define OR1200_DU_TBADR         11'h0ff
`define OR1200_DU_TBIA          11'h1xx
`define OR1200_DU_TBIA          11'h1??
`define OR1200_DU_TBIM          11'h2xx
`define OR1200_DU_TBIM          11'h2??
`define OR1200_DU_TBAR          11'h3xx
`define OR1200_DU_TBAR          11'h3??
`define OR1200_DU_TBTS          11'h4xx
`define OR1200_DU_TBTS          11'h4??
`endif
`endif
 
 
// Position of offset bits inside SPR address
// Position of offset bits inside SPR address
`define OR1200_DUOFS_BITS       10:0
`define OR1200_DUOFS_BITS       10:0
 
 
Line 1073... Line 1073...
 
 
//
//
// Shift {MACHI,MACLO} into destination register when executing l.macrc
// Shift {MACHI,MACLO} into destination register when executing l.macrc
//
//
// According to architecture manual there is no shift, so default value is 0.
// According to architecture manual there is no shift, so default value is 0.
//
// However the implementation has deviated in this from the arch manual and had
// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which
// hard coded shift by 28 bits which is a useful optimization for MP3 decoding 
// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer
// (if using libmad fixed point library). Shifts are no longer default setup, 
// default setup, but if you need to remain backward compatible, define your shift bits, which were normally
// but if you need to remain backward compatible, define your shift bits, which
 
// were normally
// dest_GPR = {MACHI,MACLO}[59:28]
// dest_GPR = {MACHI,MACLO}[59:28]
`define OR1200_MAC_SHIFTBY      0        // 0 = According to arch manual, 28 = obsolete backward compatibility
`define OR1200_MAC_SHIFTBY      0        // 0 = According to arch manual, 28 = obsolete backward compatibility
 
 
 
 
//////////////////////////////////////////////
//////////////////////////////////////////////
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`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
`define OR1200_DCCFGR_RES1              17'h00000
`define OR1200_DCCFGR_RES1              17'h00000
`else
`else
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4)      // 16 byte cache block
`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block
`ifdef OR1200_DC_WRITETHROUGH
`ifdef OR1200_DC_WRITETHROUGH
 `define OR1200_DCCFGR_CWS              1'b0    // Write-through strategy
 `define OR1200_DCCFGR_CWS              1'b0    // Write-through strategy
`else
`else
 `define OR1200_DCCFGR_CWS              1'b1    // Write-back strategy
 `define OR1200_DCCFGR_CWS              1'b1    // Write-back strategy
`endif
`endif
Line 1676... Line 1677...
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
`define OR1200_ICCFGR_RES1              17'h00000
`define OR1200_ICCFGR_RES1              17'h00000
`else
`else
`define OR1200_ICCFGR_NCW               3'h0    // 1 cache way
`define OR1200_ICCFGR_NCW               3'h0    // 1 cache way
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)       // Num cache sets
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)       // Num cache sets
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4)      // 16 byte cache block
`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1  // 16 byte cache block
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
`define OR1200_ICCFGR_CCRI              1'b1    // Cache control reg impl.
`define OR1200_ICCFGR_CCRI              1'b1    // Cache control reg impl.
`define OR1200_ICCFGR_CBIRI             1'b1    // Cache block inv reg impl.
`define OR1200_ICCFGR_CBIRI             1'b1    // Cache block inv reg impl.
`define OR1200_ICCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
`define OR1200_ICCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
`define OR1200_ICCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
`define OR1200_ICCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
Line 1704... Line 1705...
`endif
`endif
`else
`else
`define OR1200_DCFGR_NDP                4'h0    // Zero DVR/DCR pairs
`define OR1200_DCFGR_NDP                4'h0    // Zero DVR/DCR pairs
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
`endif
`endif
`define OR1200_DCFGR_RES1               28'h0000000
`define OR1200_DCFGR_RES1               27'd0
 
 
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// Boot Address Selection                                                    //
// Boot Address Selection                                                    //
// This only changes where the initial reset occurs. EPH setting is still    //
// This only changes where the initial reset occurs. EPH setting is still    //
// used to determine where vectors are located.                              //
// used to determine where vectors are located.                              //

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