| Line 41... |
Line 41... |
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: or1200_dmmu_tlb.v,v $
|
|
// Revision 2.0 2010/06/30 11:00:00 ORSoC
|
|
// Minor update:
|
|
// Bugs fixed, coding style changed.
|
|
//
|
|
// Revision 1.7 2004/06/08 18:17:36 lampret
|
|
// Non-functional changes. Coding style fixes.
|
|
//
|
// Revision 1.6 2004/04/05 08:29:57 lampret
|
// Revision 1.6 2004/04/05 08:29:57 lampret
|
// Merged branch_qmem into main tree.
|
// Merged branch_qmem into main tree.
|
//
|
//
|
// Revision 1.4.4.1 2003/12/09 11:46:48 simons
|
// Revision 1.4.4.1 2003/12/09 11:46:48 simons
|
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
|
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
|
| Line 202... |
Line 209... |
|
|
//
|
//
|
// Output to SPRS unit
|
// Output to SPRS unit
|
//
|
//
|
assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR]) ?
|
assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR]) ?
|
{vpn, tlb_index & {`OR1200_DTLB_INDXW{v}}, {`OR1200_DTLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
|
{vpn, tlb_index, {`OR1200_DTLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
|
(spr_cs & !spr_write & spr_addr[`OR1200_DTLB_TM_ADDR]) ?
|
(spr_cs & !spr_write & spr_addr[`OR1200_DTLB_TM_ADDR]) ?
|
{ppn, {`OR1200_DMMU_PS-10{1'b0}}, swe, sre, uwe, ure, {4{1'b0}}, ci, 1'b0} :
|
{ppn, {`OR1200_DMMU_PS-10{1'b0}}, swe, sre, uwe, ure, {4{1'b0}}, ci, 1'b0} :
|
32'h00000000;
|
32'h00000000;
|
|
|
//
|
//
|
| Line 246... |
Line 253... |
assign tlb_index = spr_cs ? spr_addr[`OR1200_DTLB_INDXW-1:0] : vaddr[`OR1200_DTLB_INDX];
|
assign tlb_index = spr_cs ? spr_addr[`OR1200_DTLB_INDXW-1:0] : vaddr[`OR1200_DTLB_INDX];
|
|
|
//
|
//
|
// Instantiation of DTLB Match Registers
|
// Instantiation of DTLB Match Registers
|
//
|
//
|
or1200_spram_64x14 dtlb_mr_ram(
|
//or1200_spram_64x14 dtlb_mr_ram(
|
|
or1200_spram #
|
|
(
|
|
.aw(6),
|
|
.dw(14)
|
|
)
|
|
dtlb_ram
|
|
(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
.mbist_si_i(mbist_mr_si),
|
.mbist_si_i(mbist_mr_si),
|
.mbist_so_o(mbist_mr_so),
|
.mbist_so_o(mbist_mr_so),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
`endif
|
`endif
|
.ce(tlb_mr_en),
|
.ce(tlb_mr_en),
|
.we(tlb_mr_we),
|
.we(tlb_mr_we),
|
.oe(1'b1),
|
|
.addr(tlb_index),
|
.addr(tlb_index),
|
.di(tlb_mr_ram_in),
|
.di(tlb_mr_ram_in),
|
.doq(tlb_mr_ram_out)
|
.doq(tlb_mr_ram_out)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of DTLB Translate Registers
|
// Instantiation of DTLB Translate Registers
|
//
|
//
|
or1200_spram_64x24 dtlb_tr_ram(
|
//or1200_spram_64x24 dtlb_tr_ram(
|
|
or1200_spram #
|
|
(
|
|
.aw(6),
|
|
.dw(24)
|
|
)
|
|
dtlb_tr_ram
|
|
(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
.mbist_si_i(mbist_tr_si),
|
.mbist_si_i(mbist_tr_si),
|
.mbist_so_o(mbist_tr_so),
|
.mbist_so_o(mbist_tr_so),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
`endif
|
`endif
|
.ce(tlb_tr_en),
|
.ce(tlb_tr_en),
|
.we(tlb_tr_we),
|
.we(tlb_tr_we),
|
.oe(1'b1),
|
|
.addr(tlb_index),
|
.addr(tlb_index),
|
.di(tlb_tr_ram_in),
|
.di(tlb_tr_ram_in),
|
.doq(tlb_tr_ram_out)
|
.doq(tlb_tr_ram_out)
|
);
|
);
|
|
|
endmodule
|
endmodule // or1200_dmmu_tlb
|
|
|
No newline at end of file
|
No newline at end of file
|
