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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Data TLB ////
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//// OR1200's Data TLB ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Instantiation of DTLB. ////
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//// Instantiation of DTLB. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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//
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//
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// $Log: or1200_dmmu_tlb.v,v $
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// $Log: or1200_dmmu_tlb.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Minor update:
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// Bugs fixed, coding style changed.
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// Bugs fixed, coding style changed.
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//
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//
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// Revision 1.7 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.6 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.4.4.1 2003/12/09 11:46:48 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.4 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.3 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.2 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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