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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dmmu_top.v] - Diff between revs 258 and 358

Rev 258	Rev 358
Line 204...	Line 204...
`assign dcpu_err_o = miss \| fault \| qmemdmmu_err_i;`	`assign dcpu_err_o = miss \| fault \| qmemdmmu_err_i;`

`//`	`//`
`// Assert dtlb_done one clock cycle after new address and dtlb_en must be active`	`// Assert dtlb_done one clock cycle after new address and dtlb_en must be active`
`//`	`//`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dtlb_done <= 1'b0;`	`dtlb_done <= 1'b0;`
`else if (dtlb_en)`	`else if (dtlb_en)`
`dtlb_done <= dcpu_cycstb_i;`	`dtlb_done <= dcpu_cycstb_i;`
`else`	`else`
`dtlb_done <= 1'b0;`	`dtlb_done <= 1'b0;`
Line 229...	Line 229...

`//`	`//`
`// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is`	`// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is`
`// expected to come one clock cycle after offset part.`	`// expected to come one clock cycle after offset part.`
`//`	`//`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
dcpu_vpn_r <= {31-`OR1200_DMMU_PS{1'b0}};	dcpu_vpn_r <= {31-`OR1200_DMMU_PS{1'b0}};
`else`	`else`
dcpu_vpn_r <= dcpu_adr_i[31:`OR1200_DMMU_PS];	dcpu_vpn_r <= dcpu_adr_i[31:`OR1200_DMMU_PS];

`//`	`//`