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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dmmu_top.v] - Diff between revs 10 and 141

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Rev 10 Rev 141
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//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: or1200_dmmu_top.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Minor update: 
 
// Bugs fixed. 
 
//
 
// Revision 1.9  2004/04/05 08:29:57  lampret
 
// Merged branch_qmem into main tree.
 
//
// Revision 1.7.4.2  2003/12/09 11:46:48  simons
// Revision 1.7.4.2  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
//
// Revision 1.7.4.1  2003/07/08 15:36:37  lampret
// Revision 1.7.4.1  2003/07/08 15:36:37  lampret
// Added embedded memory QMEM.
// Added embedded memory QMEM.
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//assign qmemdmmu_cycstb_o = (dmmu_en) ? ~(miss | fault) & dcpu_cycstb_i : (miss | fault) ? 1'b0 : dcpu_cycstb_i;
//assign qmemdmmu_cycstb_o = (dmmu_en) ? ~(miss | fault) & dcpu_cycstb_i : (miss | fault) ? 1'b0 : dcpu_cycstb_i;
 
 
//
//
// Cache Inhibit
// Cache Inhibit
//
//
assign qmemdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : `OR1200_DMMU_CI;
//assign qmemdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : `OR1200_DMMU_CI;
 
assign qmemdmmu_ci_o = dmmu_en ? dtlb_ci : `OR1200_DMMU_CI;
 
 
//
//
// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is expected to come
// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is expected to come
// one clock cycle after offset part.
// one clock cycle after offset part.
//
//

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