| Line 102... |
Line 102... |
// from the simulator, since it has an input (as required by IEEE 1364-2001).
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// from the simulator, since it has an input (as required by IEEE 1364-2001).
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function [31:0] get_gpr;
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function [31:0] get_gpr;
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// verilator public
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// verilator public
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input [aw-1:0] gpr_no;
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input [aw-1:0] gpr_no;
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|
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get_gpr = { mem[gpr_no*32 + 31], mem[gpr_no*32 + 30],
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get_gpr = mem[gpr_no];
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mem[gpr_no*32 + 29], mem[gpr_no*32 + 28],
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mem[gpr_no*32 + 27], mem[gpr_no*32 + 26],
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mem[gpr_no*32 + 25], mem[gpr_no*32 + 24],
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mem[gpr_no*32 + 23], mem[gpr_no*32 + 22],
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mem[gpr_no*32 + 21], mem[gpr_no*32 + 20],
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mem[gpr_no*32 + 19], mem[gpr_no*32 + 18],
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mem[gpr_no*32 + 17], mem[gpr_no*32 + 16],
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mem[gpr_no*32 + 15], mem[gpr_no*32 + 14],
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mem[gpr_no*32 + 13], mem[gpr_no*32 + 12],
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mem[gpr_no*32 + 11], mem[gpr_no*32 + 10],
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mem[gpr_no*32 + 9], mem[gpr_no*32 + 8],
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mem[gpr_no*32 + 7], mem[gpr_no*32 + 6],
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mem[gpr_no*32 + 5], mem[gpr_no*32 + 4],
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mem[gpr_no*32 + 3], mem[gpr_no*32 + 2],
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mem[gpr_no*32 + 1], mem[gpr_no*32 + 0] };
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endfunction // get_gpr
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endfunction // get_gpr
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//
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//
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// Data output drivers
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// Data output drivers
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| Line 133... |
Line 118... |
//
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//
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// RAM read
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// RAM read
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//
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//
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always @(posedge clk_a)
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always @(posedge clk_a)
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if (ce_a)
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if (ce_a)
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addr_a_reg <= #1 addr_a;
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addr_a_reg <= addr_a;
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//
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//
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// RAM write
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// RAM write
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//
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//
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always @(posedge clk_b)
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always @(posedge clk_b)
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if (ce_b & we_b)
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if (ce_b & we_b)
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mem[addr_b] <= #1 di_b;
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mem[addr_b] <= di_b;
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endmodule // or1200_dpram
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endmodule // or1200_dpram
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No newline at end of file
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No newline at end of file
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