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//
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//
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//
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//
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// Generic RAM's registers and wires
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// Generic RAM's registers and wires
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//
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//
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reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
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reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/; // RAM content
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reg [aw-1:0] addr_a_reg; // RAM address registered
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reg [aw-1:0] addr_a_reg; // RAM address registered
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// Function to access GPRs (for use by Verilator). No need to hide this one
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// Function to access GPRs (for use by Verilator). No need to hide this one
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// from the simulator, since it has an input (as required by IEEE 1364-2001).
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// from the simulator, since it has an input (as required by IEEE 1364-2001).
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