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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dpram.v] - Diff between revs 142 and 151

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Rev 142 Rev 151
Line 92... Line 92...
   //
   //
 
 
   //
   //
   // Generic RAM's registers and wires
   // Generic RAM's registers and wires
   //
   //
   reg [dw-1:0]          mem [(1<<aw)-1:0];       // RAM content
   reg [dw-1:0]          mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;    // RAM content
   reg [aw-1:0]          addr_a_reg;             // RAM address registered
   reg [aw-1:0]          addr_a_reg;             // RAM address registered
 
 
 
 
   // Function to access GPRs (for use by Verilator). No need to hide this one
   // Function to access GPRs (for use by Verilator). No need to hide this one
   // from the simulator, since it has an input (as required by IEEE 1364-2001).
   // from the simulator, since it has an input (as required by IEEE 1364-2001).

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