OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dpram.v] - Diff between revs 151 and 258

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 151 Rev 258
Line 102... Line 102...
   // from the simulator, since it has an input (as required by IEEE 1364-2001).
   // from the simulator, since it has an input (as required by IEEE 1364-2001).
   function [31:0] get_gpr;
   function [31:0] get_gpr;
      // verilator public
      // verilator public
      input [aw-1:0]             gpr_no;
      input [aw-1:0]             gpr_no;
 
 
      get_gpr = { mem[gpr_no*32 + 31], mem[gpr_no*32 + 30],
      get_gpr = mem[gpr_no];
                  mem[gpr_no*32 + 29], mem[gpr_no*32 + 28],
 
                  mem[gpr_no*32 + 27], mem[gpr_no*32 + 26],
 
                  mem[gpr_no*32 + 25], mem[gpr_no*32 + 24],
 
                  mem[gpr_no*32 + 23], mem[gpr_no*32 + 22],
 
                  mem[gpr_no*32 + 21], mem[gpr_no*32 + 20],
 
                  mem[gpr_no*32 + 19], mem[gpr_no*32 + 18],
 
                  mem[gpr_no*32 + 17], mem[gpr_no*32 + 16],
 
                  mem[gpr_no*32 + 15], mem[gpr_no*32 + 14],
 
                  mem[gpr_no*32 + 13], mem[gpr_no*32 + 12],
 
                  mem[gpr_no*32 + 11], mem[gpr_no*32 + 10],
 
                  mem[gpr_no*32 +  9], mem[gpr_no*32 +  8],
 
                  mem[gpr_no*32 +  7], mem[gpr_no*32 +  6],
 
                  mem[gpr_no*32 +  5], mem[gpr_no*32 +  4],
 
                  mem[gpr_no*32 +  3], mem[gpr_no*32 +  2],
 
                  mem[gpr_no*32 +  1], mem[gpr_no*32 +  0] };
 
 
 
   endfunction // get_gpr
   endfunction // get_gpr
 
 
   //
   //
   // Data output drivers
   // Data output drivers
Line 133... Line 118...
   //
   //
   // RAM read
   // RAM read
   //
   //
   always @(posedge clk_a)
   always @(posedge clk_a)
     if (ce_a)
     if (ce_a)
       addr_a_reg <= #1 addr_a;
       addr_a_reg <=  addr_a;
 
 
   //
   //
   // RAM write
   // RAM write
   //
   //
   always @(posedge clk_b)
   always @(posedge clk_b)
     if (ce_b & we_b)
     if (ce_b & we_b)
       mem[addr_b] <= #1 di_b;
       mem[addr_b] <=  di_b;
 
 
endmodule // or1200_dpram
endmodule // or1200_dpram
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.