OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dpram_256x32.v] - Diff between revs 258 and 358

Show entire file | Details | Blame | View Log

Rev 258 Rev 358
Line 198... Line 198...
assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
 
 
//
//
// RAM read
// RAM read
//
//
always @(posedge clk_a or posedge rst_a)
always @(posedge clk_a or `OR1200_RST_EVENT rst_a)
        if (rst_a)
        if (rst_a == `OR1200_RST_VALUE)
                addr_a_reg <=  {aw{1'b0}};
                addr_a_reg <=  {aw{1'b0}};
        else if (ce_a)
        else if (ce_a)
                addr_a_reg <=  addr_a;
                addr_a_reg <=  addr_a;
 
 
//
//

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.