URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dpram_256x32.v] - Diff between revs 141 and 258

Rev 141	Rev 258
Line 200...	Line 200...
`//`	`//`
`// RAM read`	`// RAM read`
`//`	`//`
`always @(posedge clk_a or posedge rst_a)`	`always @(posedge clk_a or posedge rst_a)`
`if (rst_a)`	`if (rst_a)`
`addr_a_reg <= #1 {aw{1'b0}};`	`addr_a_reg <= {aw{1'b0}};`
`else if (ce_a)`	`else if (ce_a)`
`addr_a_reg <= #1 addr_a;`	`addr_a_reg <= addr_a;`

`//`	`//`
`// RAM write`	`// RAM write`
`//`	`//`
`always @(posedge clk_b)`	`always @(posedge clk_b)`
`if (ce_b && we_b)`	`if (ce_b && we_b)`
`mem[addr_b] <= #1 di_b;`	`mem[addr_b] <= di_b;`

`endif // !OR1200_XILINX_RAMB16	`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4	`endif // !OR1200_XILINX_RAMB4
`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`