URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Diff between revs 258 and 358

Rev 258	Rev 358
Line 307...	Line 307...
`// Virtex/Spartan2`	`// Virtex/Spartan2`
`//`	`//`

`reg [4:0] addr_a_r;`	`reg [4:0] addr_a_r;`

`always @(posedge clk_a or posedge rst_a)`	always @(posedge clk_a or `OR1200_RST_EVENT rst_a)
`if (rst_a)`	if (rst_a == `OR1200_RST_VALUE)
`addr_a_r <= 5'b00000;`	`addr_a_r <= 5'b00000;`
`else if (ce_a)`	`else if (ce_a)`
`addr_a_r <= addr_a;`	`addr_a_r <= addr_a;`

`//`	`//`
Line 530...	Line 530...
`assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};`	`assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};`

`//`	`//`
`// RAM read`	`// RAM read`
`//`	`//`
`always @(posedge clk_a or posedge rst_a)`	always @(posedge clk_a or `OR1200_RST_EVENT rst_a)
`if (rst_a)`	if (rst_a == `OR1200_RST_VALUE)
`addr_a_reg <= {aw{1'b0}};`	`addr_a_reg <= {aw{1'b0}};`
`else if (ce_a)`	`else if (ce_a)`
`addr_a_reg <= addr_a;`	`addr_a_reg <= addr_a;`

`//`	`//`