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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Diff between revs 141 and 258

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Rev 141 Rev 258
Line 309... Line 309...
 
 
reg     [4:0]    addr_a_r;
reg     [4:0]    addr_a_r;
 
 
always @(posedge clk_a or posedge rst_a)
always @(posedge clk_a or posedge rst_a)
        if (rst_a)
        if (rst_a)
                addr_a_r <= #1 5'b00000;
                addr_a_r <=  5'b00000;
        else if (ce_a)
        else if (ce_a)
                addr_a_r <= #1 addr_a;
                addr_a_r <=  addr_a;
 
 
//
//
// Block 0
// Block 0
//
//
or1200_xcv_ram32x8d xcv_ram32x8d_0 (
or1200_xcv_ram32x8d xcv_ram32x8d_0 (
Line 532... Line 532...
//
//
// RAM read
// RAM read
//
//
always @(posedge clk_a or posedge rst_a)
always @(posedge clk_a or posedge rst_a)
        if (rst_a)
        if (rst_a)
                addr_a_reg <= #1 {aw{1'b0}};
                addr_a_reg <=  {aw{1'b0}};
        else if (ce_a)
        else if (ce_a)
                addr_a_reg <= #1 addr_a;
                addr_a_reg <=  addr_a;
 
 
//
//
// RAM write
// RAM write
//
//
always @(posedge clk_b)
always @(posedge clk_b)
        if (ce_b && we_b)
        if (ce_b && we_b)
                mem[addr_b] <= #1 di_b;
                mem[addr_b] <=  di_b;
 
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_XILINX_RAM32X1D
`endif  // !OR1200_XILINX_RAM32X1D

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