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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Debug Unit ////
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//// OR1200's Debug Unit ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Basic OR1200 debug unit. ////
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//// Basic OR1200 debug unit. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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//
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//
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// $Log: or1200_du.v,v $
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// $Log: or1200_du.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Minor update:
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// Bugs fixed.
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// Bugs fixed.
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//
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// Revision 1.12 2005/10/19 11:37:56 jcastillo
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// Added support for RAMB16 Xilinx4/Spartan3 primitives
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//
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// Revision 1.11 2005/01/07 09:35:08 andreje
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// du_hwbkpt disabled when debug unit not implemented
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//
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// Revision 1.10 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.9.4.4 2004/02/11 01:40:11 lampret
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// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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//
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// Revision 1.9.4.3 2004/01/18 10:08:00 simons
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// Error fixed.
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//
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// Revision 1.9.4.2 2004/01/17 21:14:14 simons
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// Errors fixed.
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//
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// Revision 1.9.4.1 2004/01/15 06:46:38 markom
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// interface to debug changed; no more opselect; stb-ack protocol
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//
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// Revision 1.9 2003/01/22 03:23:47 lampret
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// Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]
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//
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// Revision 1.8 2002/09/08 19:31:52 lampret
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// Fixed a typo, reported by Taylor Su.
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//
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// Revision 1.7 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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// Revision 1.6 2002/03/14 00:30:24 lampret
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// Added alternative for critical path in DU.
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.4 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.3 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.12 2001/11/30 18:58:00 simons
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// Trap insn couses break after exits ex_insn.
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//
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// Revision 1.11 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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//
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// Revision 1.10 2001/11/20 21:25:44 lampret
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// Fixed dbg_is_o assignment width.
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//
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// Revision 1.9 2001/11/20 18:46:14 simons
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// Break point bug fixed
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//
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// Revision 1.8 2001/11/18 08:36:28 lampret
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// For GDB changed single stepping and disabled trap exception.
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//
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// Revision 1.7 2001/10/21 18:09:53 lampret
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// Fixed sensitivity list.
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//
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// Revision 1.6 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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output [aw-1:0] du_addr; // Debug Unit Address
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output [aw-1:0] du_addr; // Debug Unit Address
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input [dw-1:0] du_dat_i; // Debug Unit Data In
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input [dw-1:0] du_dat_i; // Debug Unit Data In
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output [dw-1:0] du_dat_o; // Debug Unit Data Out
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output [dw-1:0] du_dat_o; // Debug Unit Data Out
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output du_read; // Debug Unit Read Enable
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output du_read; // Debug Unit Read Enable
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output du_write; // Debug Unit Write Enable
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output du_write; // Debug Unit Write Enable
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input [12:0] du_except_stop; // Exception masked by DSR
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input [13:0] du_except_stop; // Exception masked by DSR
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output du_hwbkpt; // Cause trap exception (HW Breakpoints)
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output du_hwbkpt; // Cause trap exception (HW Breakpoints)
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input spr_cs; // SPR Chip Select
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input spr_cs; // SPR Chip Select
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input spr_write; // SPR Read/Write
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input spr_write; // SPR Read/Write
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input [aw-1:0] spr_addr; // SPR Address
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input [aw-1:0] spr_addr; // SPR Address
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input [dw-1:0] spr_dat_i; // SPR Data Input
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input [dw-1:0] spr_dat_i; // SPR Data Input
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`endif
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`endif
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//
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//
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// Decode started exception
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// Decode started exception
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//
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//
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// du_except_stop comes from or1200_except
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//
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always @(du_except_stop) begin
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always @(du_except_stop) begin
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except_stop = 14'b0000_0000_0000;
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except_stop = 14'b00_0000_0000_0000;
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casex (du_except_stop)
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casex (du_except_stop)
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13'b1_xxxx_xxxx_xxxx: begin
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14'b1x_xxxx_xxxx_xxxx:
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except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
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except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
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end
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14'b01_xxxx_xxxx_xxxx: begin
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13'b0_1xxx_xxxx_xxxx: begin
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except_stop[`OR1200_DU_DRR_IE] = 1'b1;
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except_stop[`OR1200_DU_DRR_IE] = 1'b1;
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end
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end
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13'b0_01xx_xxxx_xxxx: begin
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14'b00_1xxx_xxxx_xxxx: begin
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except_stop[`OR1200_DU_DRR_IME] = 1'b1;
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except_stop[`OR1200_DU_DRR_IME] = 1'b1;
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end
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end
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13'b0_001x_xxxx_xxxx: begin
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14'b00_01xx_xxxx_xxxx:
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except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
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except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
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end
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14'b00_001x_xxxx_xxxx: begin
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13'b0_0001_xxxx_xxxx: begin
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except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
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except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
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end
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end
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13'b0_0000_1xxx_xxxx: begin
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14'b00_0001_xxxx_xxxx:
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except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
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except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
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end
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14'b00_0000_1xxx_xxxx: begin
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13'b0_0000_01xx_xxxx: begin
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except_stop[`OR1200_DU_DRR_AE] = 1'b1;
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except_stop[`OR1200_DU_DRR_AE] = 1'b1;
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end
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end
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13'b0_0000_001x_xxxx: begin
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14'b00_0000_01xx_xxxx: begin
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except_stop[`OR1200_DU_DRR_DME] = 1'b1;
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except_stop[`OR1200_DU_DRR_DME] = 1'b1;
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end
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end
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13'b0_0000_0001_xxxx: begin
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14'b00_0000_001x_xxxx:
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except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
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except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
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end
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14'b00_0000_0001_xxxx:
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13'b0_0000_0000_1xxx: begin
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except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
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except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
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end
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14'b00_0000_0000_1xxx: begin
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13'b0_0000_0000_01xx: begin
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except_stop[`OR1200_DU_DRR_RE] = 1'b1;
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except_stop[`OR1200_DU_DRR_RE] = 1'b1;
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end
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end
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13'b0_0000_0000_001x: begin
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14'b00_0000_0000_01xx: begin
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except_stop[`OR1200_DU_DRR_TE] = 1'b1;
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except_stop[`OR1200_DU_DRR_TE] = 1'b1;
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end
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end
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13'b0_0000_0000_0001: begin
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14'b00_0000_0000_001x: begin
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except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
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except_stop[`OR1200_DU_DRR_FPE] = 1'b1;
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end
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end
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14'b00_0000_0000_0001:
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except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
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default:
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default:
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except_stop = 14'b0000_0000_0000;
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except_stop = 14'b00_0000_0000_0000;
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endcase
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endcase
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end
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end
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//
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//
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// dbg_bp_o is registered
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// dbg_bp_o is registered
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