| Line 410... |
Line 410... |
dcr6_sel,
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dcr6_sel,
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dcr7_sel; // DCR selects
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dcr7_sel; // DCR selects
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wire dwcr0_sel,
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wire dwcr0_sel,
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dwcr1_sel; // DWCR selects
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dwcr1_sel; // DWCR selects
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reg dbg_bp_r;
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reg dbg_bp_r;
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reg ex_freeze_q;
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`ifdef OR1200_DU_HWBKPTS
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`ifdef OR1200_DU_HWBKPTS
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reg [31:0] match_cond0_ct;
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reg [31:0] match_cond0_ct;
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reg [31:0] match_cond1_ct;
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reg [31:0] match_cond1_ct;
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reg [31:0] match_cond2_ct;
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reg [31:0] match_cond2_ct;
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reg [31:0] match_cond3_ct;
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reg [31:0] match_cond3_ct;
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| Line 527... |
Line 528... |
`endif
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`endif
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`ifdef OR1200_DU_DWCR1
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`ifdef OR1200_DU_DWCR1
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assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
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assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
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`endif
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`endif
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|
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// Track previous ex_freeze to detect when signals are updated
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always @(posedge clk)
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ex_freeze_q <= ex_freeze;
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|
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//
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//
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// Decode started exception
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// Decode started exception
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//
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//
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// du_except_stop comes from or1200_except
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// du_except_stop comes from or1200_except
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//
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//
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always @(du_except_stop) begin
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always @(du_except_stop or ex_freeze_q) begin
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except_stop = 14'b00_0000_0000_0000;
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except_stop = 14'b00_0000_0000_0000;
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casez (du_except_stop)
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casez (du_except_stop)
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14'b1?_????_????_????:
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14'b1?_????_????_????:
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except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
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except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
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14'b01_????_????_????: begin
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14'b01_????_????_????: begin
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| Line 564... |
Line 569... |
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
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except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
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14'b00_0000_0000_1???: begin
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14'b00_0000_0000_1???: begin
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except_stop[`OR1200_DU_DRR_RE] = 1'b1;
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except_stop[`OR1200_DU_DRR_RE] = 1'b1;
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end
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end
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14'b00_0000_0000_01??: begin
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14'b00_0000_0000_01??: begin
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except_stop[`OR1200_DU_DRR_TE] = 1'b1;
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except_stop[`OR1200_DU_DRR_TE] = 1'b1 & ~ex_freeze_q;
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end
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end
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14'b00_0000_0000_001?: begin
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14'b00_0000_0000_001?: begin
|
except_stop[`OR1200_DU_DRR_FPE] = 1'b1;
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except_stop[`OR1200_DU_DRR_FPE] = 1'b1;
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end
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end
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14'b00_0000_0000_0001:
|
14'b00_0000_0000_0001:
|
except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_SCE] = 1'b1 & ~ex_freeze_q;
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default:
|
default:
|
except_stop = 14'b00_0000_0000_0000;
|
except_stop = 14'b00_0000_0000_0000;
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endcase
|
endcase // casez (du_except_stop)
|
end
|
end
|
|
|
//
|
//
|
// dbg_bp_o is registered
|
// dbg_bp_o is registered
|
//
|
//
|
