| Line 62... |
Line 62... |
dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
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dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
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dcpu_dat_dc, icpu_cycstb_i,
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dcpu_dat_dc, icpu_cycstb_i,
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ex_freeze, branch_op, ex_insn, id_pc,
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ex_freeze, branch_op, ex_insn, id_pc,
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spr_dat_npc, rf_dataw,
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spr_dat_npc, rf_dataw,
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du_dsr, du_dmr1, du_stall, du_addr, du_dat_i, du_dat_o,
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du_dsr, du_dmr1, du_stall, du_addr, du_dat_i, du_dat_o,
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du_read, du_write, du_except_stop, du_hwbkpt,
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du_read, du_write, du_except_stop, du_hwbkpt, du_flush_pipe,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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// External Debug Interface
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// External Debug Interface
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dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
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dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
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dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
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dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
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| Line 104... |
Line 104... |
output [dw-1:0] du_dat_o; // Debug Unit Data Out
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output [dw-1:0] du_dat_o; // Debug Unit Data Out
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output du_read; // Debug Unit Read Enable
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output du_read; // Debug Unit Read Enable
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output du_write; // Debug Unit Write Enable
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output du_write; // Debug Unit Write Enable
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input [13:0] du_except_stop; // Exception masked by DSR
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input [13:0] du_except_stop; // Exception masked by DSR
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output du_hwbkpt; // Cause trap exception (HW Breakpoints)
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output du_hwbkpt; // Cause trap exception (HW Breakpoints)
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output du_flush_pipe; // Cause pipeline flush and pc<-npc
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input spr_cs; // SPR Chip Select
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input spr_cs; // SPR Chip Select
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input spr_write; // SPR Read/Write
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input spr_write; // SPR Read/Write
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input [aw-1:0] spr_addr; // SPR Address
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input [aw-1:0] spr_addr; // SPR Address
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input [dw-1:0] spr_dat_i; // SPR Data Input
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input [dw-1:0] spr_dat_i; // SPR Data Input
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output [dw-1:0] spr_dat_o; // SPR Data Output
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output [dw-1:0] spr_dat_o; // SPR Data Output
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| Line 162... |
Line 163... |
assign du_addr = dbg_adr_i;
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assign du_addr = dbg_adr_i;
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assign du_dat_o = dbg_dat_i;
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assign du_dat_o = dbg_dat_i;
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assign du_read = dbg_stb_i && !dbg_we_i;
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assign du_read = dbg_stb_i && !dbg_we_i;
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assign du_write = dbg_stb_i && dbg_we_i;
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assign du_write = dbg_stb_i && dbg_we_i;
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//
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// After a sw breakpoint, the replaced instruction need to be executed.
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// We flush the entire pipeline and set the pc to the current address
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// to execute the restored address.
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//
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reg du_flush_pipe_r;
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reg dbg_stall_i_r;
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assign du_flush_pipe = du_flush_pipe_r;
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//
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// Register du_flush_pipe
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//
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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if (rst == `OR1200_RST_VALUE) begin
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du_flush_pipe_r <= 1'b0;
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end
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else begin
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du_flush_pipe_r <= (dbg_stall_i_r && !dbg_stall_i && |du_except_stop);
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end
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end
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//
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// Detect dbg_stall falling edge
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//
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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if (rst == `OR1200_RST_VALUE) begin
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dbg_stall_i_r <= 1'b0;
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end
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else begin
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dbg_stall_i_r <= dbg_stall_i;
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end
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end
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reg dbg_ack;
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reg dbg_ack;
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//
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//
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// Generate acknowledge -- just delay stb signal
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// Generate acknowledge -- just delay stb signal
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//
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//
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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