OpenCores

Rev 258	Rev 358
Line 139...	Line 139...

`reg [1:0] dbg_is_o;`	`reg [1:0] dbg_is_o;`
`//`	`//`
`// Show insn activity (temp, must be removed)`	`// Show insn activity (temp, must be removed)`
`//`	`//`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dbg_is_o <= 2'b00;`	`dbg_is_o <= 2'b00;`
else if (!ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))	else if (!ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
`dbg_is_o <= ~dbg_is_o;`	`dbg_is_o <= ~dbg_is_o;`
`ifdef UNUSED	`ifdef UNUSED
`assign dbg_is_o = 2'b00;`	`assign dbg_is_o = 2'b00;`
Line 166...	Line 166...

`reg dbg_ack;`	`reg dbg_ack;`
`//`	`//`
`// Generate acknowledge -- just delay stb signal`	`// Generate acknowledge -- just delay stb signal`
`//`	`//`
`always @(posedge clk or posedge rst) begin`	always @(posedge clk or `OR1200_RST_EVENT rst) begin
`if (rst) begin`	if (rst == `OR1200_RST_VALUE) begin
`dbg_ack <= 1'b0;`	`dbg_ack <= 1'b0;`
`dbg_ack_o <= 1'b0;`	`dbg_ack_o <= 1'b0;`
`end`	`end`
`else begin`	`else begin`
`dbg_ack <= dbg_stb_i; // valid when du_dat_i`	`dbg_ack <= dbg_stb_i; // valid when du_dat_i`
Line 584...	Line 584...
`assign dbg_bp_o = dbg_bp_r;`	`assign dbg_bp_o = dbg_bp_r;`

`//`	`//`
`// Breakpoint activation register`	`// Breakpoint activation register`
`//`	`//`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dbg_bp_r <= 1'b0;`	`dbg_bp_r <= 1'b0;`
`else if (!ex_freeze)`	`else if (!ex_freeze)`
`dbg_bp_r <= \|except_stop`	`dbg_bp_r <= \|except_stop`
`ifdef OR1200_DU_DMR1_ST	`ifdef OR1200_DU_DMR1_ST
\| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]	\| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
Line 603...	Line 603...

`//`	`//`
`// Write to DMR1`	`// Write to DMR1`
`//`	`//`
`ifdef OR1200_DU_DMR1	`ifdef OR1200_DU_DMR1
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dmr1 <= 25'h000_0000;`	`dmr1 <= 25'h000_0000;`
`else if (dmr1_sel && spr_write)`	`else if (dmr1_sel && spr_write)`
`ifdef OR1200_DU_HWBKPTS	`ifdef OR1200_DU_HWBKPTS
`dmr1 <= spr_dat_i[24:0];`	`dmr1 <= spr_dat_i[24:0];`
`else	`else
Line 620...	Line 620...

`//`	`//`
`// Write to DMR2`	`// Write to DMR2`
`//`	`//`
`ifdef OR1200_DU_DMR2	`ifdef OR1200_DU_DMR2
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dmr2 <= 24'h00_0000;`	`dmr2 <= 24'h00_0000;`
`else if (dmr2_sel && spr_write)`	`else if (dmr2_sel && spr_write)`
`dmr2 <= spr_dat_i[23:0];`	`dmr2 <= spr_dat_i[23:0];`
`else	`else
`assign dmr2 = 24'h00_0000;`	`assign dmr2 = 24'h00_0000;`
Line 633...	Line 633...

`//`	`//`
`// Write to DSR`	`// Write to DSR`
`//`	`//`
`ifdef OR1200_DU_DSR	`ifdef OR1200_DU_DSR
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};	dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
`else if (dsr_sel && spr_write)`	`else if (dsr_sel && spr_write)`
dsr <= spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];	dsr <= spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
`else	`else
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};	assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
Line 646...	Line 646...

`//`	`//`
`// Write to DRR`	`// Write to DRR`
`//`	`//`
`ifdef OR1200_DU_DRR	`ifdef OR1200_DU_DRR
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`drr <= 14'b0;`	`drr <= 14'b0;`
`else if (drr_sel && spr_write)`	`else if (drr_sel && spr_write)`
`drr <= spr_dat_i[13:0];`	`drr <= spr_dat_i[13:0];`
`else`	`else`
`drr <= drr \| except_stop;`	`drr <= drr \| except_stop;`
Line 661...	Line 661...

`//`	`//`
`// Write to DVR0`	`// Write to DVR0`
`//`	`//`
`ifdef OR1200_DU_DVR0	`ifdef OR1200_DU_DVR0
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dvr0 <= 32'h0000_0000;`	`dvr0 <= 32'h0000_0000;`
`else if (dvr0_sel && spr_write)`	`else if (dvr0_sel && spr_write)`
`dvr0 <= spr_dat_i[31:0];`	`dvr0 <= spr_dat_i[31:0];`
`else	`else
`assign dvr0 = 32'h0000_0000;`	`assign dvr0 = 32'h0000_0000;`
Line 674...	Line 674...

`//`	`//`
`// Write to DVR1`	`// Write to DVR1`
`//`	`//`
`ifdef OR1200_DU_DVR1	`ifdef OR1200_DU_DVR1
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dvr1 <= 32'h0000_0000;`	`dvr1 <= 32'h0000_0000;`
`else if (dvr1_sel && spr_write)`	`else if (dvr1_sel && spr_write)`
`dvr1 <= spr_dat_i[31:0];`	`dvr1 <= spr_dat_i[31:0];`
`else	`else
`assign dvr1 = 32'h0000_0000;`	`assign dvr1 = 32'h0000_0000;`
Line 687...	Line 687...

`//`	`//`
`// Write to DVR2`	`// Write to DVR2`
`//`	`//`
`ifdef OR1200_DU_DVR2	`ifdef OR1200_DU_DVR2
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dvr2 <= 32'h0000_0000;`	`dvr2 <= 32'h0000_0000;`
`else if (dvr2_sel && spr_write)`	`else if (dvr2_sel && spr_write)`
`dvr2 <= spr_dat_i[31:0];`	`dvr2 <= spr_dat_i[31:0];`
`else	`else
`assign dvr2 = 32'h0000_0000;`	`assign dvr2 = 32'h0000_0000;`
Line 700...	Line 700...

`//`	`//`
`// Write to DVR3`	`// Write to DVR3`
`//`	`//`
`ifdef OR1200_DU_DVR3	`ifdef OR1200_DU_DVR3
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dvr3 <= 32'h0000_0000;`	`dvr3 <= 32'h0000_0000;`
`else if (dvr3_sel && spr_write)`	`else if (dvr3_sel && spr_write)`
`dvr3 <= spr_dat_i[31:0];`	`dvr3 <= spr_dat_i[31:0];`
`else	`else
`assign dvr3 = 32'h0000_0000;`	`assign dvr3 = 32'h0000_0000;`
Line 713...	Line 713...

`//`	`//`
`// Write to DVR4`	`// Write to DVR4`
`//`	`//`
`ifdef OR1200_DU_DVR4	`ifdef OR1200_DU_DVR4
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dvr4 <= 32'h0000_0000;`	`dvr4 <= 32'h0000_0000;`
`else if (dvr4_sel && spr_write)`	`else if (dvr4_sel && spr_write)`
`dvr4 <= spr_dat_i[31:0];`	`dvr4 <= spr_dat_i[31:0];`
`else	`else
`assign dvr4 = 32'h0000_0000;`	`assign dvr4 = 32'h0000_0000;`
Line 726...	Line 726...

`//`	`//`
`// Write to DVR5`	`// Write to DVR5`
`//`	`//`
`ifdef OR1200_DU_DVR5	`ifdef OR1200_DU_DVR5
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dvr5 <= 32'h0000_0000;`	`dvr5 <= 32'h0000_0000;`
`else if (dvr5_sel && spr_write)`	`else if (dvr5_sel && spr_write)`
`dvr5 <= spr_dat_i[31:0];`	`dvr5 <= spr_dat_i[31:0];`
`else	`else
`assign dvr5 = 32'h0000_0000;`	`assign dvr5 = 32'h0000_0000;`
Line 739...	Line 739...

`//`	`//`
`// Write to DVR6`	`// Write to DVR6`
`//`	`//`
`ifdef OR1200_DU_DVR6	`ifdef OR1200_DU_DVR6
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dvr6 <= 32'h0000_0000;`	`dvr6 <= 32'h0000_0000;`
`else if (dvr6_sel && spr_write)`	`else if (dvr6_sel && spr_write)`
`dvr6 <= spr_dat_i[31:0];`	`dvr6 <= spr_dat_i[31:0];`
`else	`else
`assign dvr6 = 32'h0000_0000;`	`assign dvr6 = 32'h0000_0000;`
Line 752...	Line 752...

`//`	`//`
`// Write to DVR7`	`// Write to DVR7`
`//`	`//`
`ifdef OR1200_DU_DVR7	`ifdef OR1200_DU_DVR7
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dvr7 <= 32'h0000_0000;`	`dvr7 <= 32'h0000_0000;`
`else if (dvr7_sel && spr_write)`	`else if (dvr7_sel && spr_write)`
`dvr7 <= spr_dat_i[31:0];`	`dvr7 <= spr_dat_i[31:0];`
`else	`else
`assign dvr7 = 32'h0000_0000;`	`assign dvr7 = 32'h0000_0000;`
Line 765...	Line 765...

`//`	`//`
`// Write to DCR0`	`// Write to DCR0`
`//`	`//`
`ifdef OR1200_DU_DCR0	`ifdef OR1200_DU_DCR0
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dcr0 <= 8'h00;`	`dcr0 <= 8'h00;`
`else if (dcr0_sel && spr_write)`	`else if (dcr0_sel && spr_write)`
`dcr0 <= spr_dat_i[7:0];`	`dcr0 <= spr_dat_i[7:0];`
`else	`else
`assign dcr0 = 8'h00;`	`assign dcr0 = 8'h00;`
Line 778...	Line 778...

`//`	`//`
`// Write to DCR1`	`// Write to DCR1`
`//`	`//`
`ifdef OR1200_DU_DCR1	`ifdef OR1200_DU_DCR1
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dcr1 <= 8'h00;`	`dcr1 <= 8'h00;`
`else if (dcr1_sel && spr_write)`	`else if (dcr1_sel && spr_write)`
`dcr1 <= spr_dat_i[7:0];`	`dcr1 <= spr_dat_i[7:0];`
`else	`else
`assign dcr1 = 8'h00;`	`assign dcr1 = 8'h00;`
Line 791...	Line 791...

`//`	`//`
`// Write to DCR2`	`// Write to DCR2`
`//`	`//`
`ifdef OR1200_DU_DCR2	`ifdef OR1200_DU_DCR2
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dcr2 <= 8'h00;`	`dcr2 <= 8'h00;`
`else if (dcr2_sel && spr_write)`	`else if (dcr2_sel && spr_write)`
`dcr2 <= spr_dat_i[7:0];`	`dcr2 <= spr_dat_i[7:0];`
`else	`else
`assign dcr2 = 8'h00;`	`assign dcr2 = 8'h00;`
Line 804...	Line 804...

`//`	`//`
`// Write to DCR3`	`// Write to DCR3`
`//`	`//`
`ifdef OR1200_DU_DCR3	`ifdef OR1200_DU_DCR3
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dcr3 <= 8'h00;`	`dcr3 <= 8'h00;`
`else if (dcr3_sel && spr_write)`	`else if (dcr3_sel && spr_write)`
`dcr3 <= spr_dat_i[7:0];`	`dcr3 <= spr_dat_i[7:0];`
`else	`else
`assign dcr3 = 8'h00;`	`assign dcr3 = 8'h00;`
Line 817...	Line 817...

`//`	`//`
`// Write to DCR4`	`// Write to DCR4`
`//`	`//`
`ifdef OR1200_DU_DCR4	`ifdef OR1200_DU_DCR4
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dcr4 <= 8'h00;`	`dcr4 <= 8'h00;`
`else if (dcr4_sel && spr_write)`	`else if (dcr4_sel && spr_write)`
`dcr4 <= spr_dat_i[7:0];`	`dcr4 <= spr_dat_i[7:0];`
`else	`else
`assign dcr4 = 8'h00;`	`assign dcr4 = 8'h00;`
Line 830...	Line 830...

`//`	`//`
`// Write to DCR5`	`// Write to DCR5`
`//`	`//`
`ifdef OR1200_DU_DCR5	`ifdef OR1200_DU_DCR5
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dcr5 <= 8'h00;`	`dcr5 <= 8'h00;`
`else if (dcr5_sel && spr_write)`	`else if (dcr5_sel && spr_write)`
`dcr5 <= spr_dat_i[7:0];`	`dcr5 <= spr_dat_i[7:0];`
`else	`else
`assign dcr5 = 8'h00;`	`assign dcr5 = 8'h00;`
Line 843...	Line 843...

`//`	`//`
`// Write to DCR6`	`// Write to DCR6`
`//`	`//`
`ifdef OR1200_DU_DCR6	`ifdef OR1200_DU_DCR6
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dcr6 <= 8'h00;`	`dcr6 <= 8'h00;`
`else if (dcr6_sel && spr_write)`	`else if (dcr6_sel && spr_write)`
`dcr6 <= spr_dat_i[7:0];`	`dcr6 <= spr_dat_i[7:0];`
`else	`else
`assign dcr6 = 8'h00;`	`assign dcr6 = 8'h00;`
Line 856...	Line 856...

`//`	`//`
`// Write to DCR7`	`// Write to DCR7`
`//`	`//`
`ifdef OR1200_DU_DCR7	`ifdef OR1200_DU_DCR7
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dcr7 <= 8'h00;`	`dcr7 <= 8'h00;`
`else if (dcr7_sel && spr_write)`	`else if (dcr7_sel && spr_write)`
`dcr7 <= spr_dat_i[7:0];`	`dcr7 <= spr_dat_i[7:0];`
`else	`else
`assign dcr7 = 8'h00;`	`assign dcr7 = 8'h00;`
Line 869...	Line 869...

`//`	`//`
`// Write to DWCR0`	`// Write to DWCR0`
`//`	`//`
`ifdef OR1200_DU_DWCR0	`ifdef OR1200_DU_DWCR0
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dwcr0 <= 32'h0000_0000;`	`dwcr0 <= 32'h0000_0000;`
`else if (dwcr0_sel && spr_write)`	`else if (dwcr0_sel && spr_write)`
`dwcr0 <= spr_dat_i[31:0];`	`dwcr0 <= spr_dat_i[31:0];`
`else if (incr_wpcntr0)`	`else if (incr_wpcntr0)`
dwcr0[`OR1200_DU_DWCR_COUNT] <= dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;	dwcr0[`OR1200_DU_DWCR_COUNT] <= dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
Line 884...	Line 884...

`//`	`//`
`// Write to DWCR1`	`// Write to DWCR1`
`//`	`//`
`ifdef OR1200_DU_DWCR1	`ifdef OR1200_DU_DWCR1
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`dwcr1 <= 32'h0000_0000;`	`dwcr1 <= 32'h0000_0000;`
`else if (dwcr1_sel && spr_write)`	`else if (dwcr1_sel && spr_write)`
`dwcr1 <= spr_dat_i[31:0];`	`dwcr1 <= spr_dat_i[31:0];`
`else if (incr_wpcntr1)`	`else if (incr_wpcntr1)`
dwcr1[`OR1200_DU_DWCR_COUNT] <= dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;	dwcr1[`OR1200_DU_DWCR_COUNT] <= dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
Line 1618...	Line 1618...
`else	`else
`assign du_hwbkpt = 1'b0;`	`assign du_hwbkpt = 1'b0;`
`endif	`endif

`// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception`	`// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`du_hwbkpt_hold <= 1'b0;`	`du_hwbkpt_hold <= 1'b0;`
`else if (du_hwbkpt & ex_freeze)`	`else if (du_hwbkpt & ex_freeze)`
`du_hwbkpt_hold <= 1'b1;`	`du_hwbkpt_hold <= 1'b1;`
`else if (!ex_freeze)`	`else if (!ex_freeze)`
`du_hwbkpt_hold <= 1'b0;`	`du_hwbkpt_hold <= 1'b0;`
Line 1643...	Line 1643...
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);	assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);

`//`	`//`
`// Trace buffer write address pointer`	`// Trace buffer write address pointer`
`//`	`//`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`tb_wadr <= 8'h00;`	`tb_wadr <= 8'h00;`
`else if (tb_enw)`	`else if (tb_enw)`
`tb_wadr <= tb_wadr + 8'd1;`	`tb_wadr <= tb_wadr + 8'd1;`

`//`	`//`
`// Free running counter (time stamp)`	`// Free running counter (time stamp)`
`//`	`//`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`tb_timstmp <= 32'h00000000;`	`tb_timstmp <= 32'h00000000;`
`else if (!dbg_bp_r)`	`else if (!dbg_bp_r)`
`tb_timstmp <= tb_timstmp + 32'd1;`	`tb_timstmp <= tb_timstmp + 32'd1;`

`//`	`//`

Line 139...

reg     [1:0]                    dbg_is_o;

reg     [1:0]                    dbg_is_o;

//

//

// Show insn activity (temp, must be removed)

// Show insn activity (temp, must be removed)

//

//

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dbg_is_o <=  2'b00;

                dbg_is_o <=  2'b00;

        else if (!ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))

        else if (!ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))

                dbg_is_o <=  ~dbg_is_o;

                dbg_is_o <=  ~dbg_is_o;

`ifdef UNUSED

`ifdef UNUSED

assign dbg_is_o = 2'b00;

assign dbg_is_o = 2'b00;

Line 166...

reg                             dbg_ack;

reg                             dbg_ack;

//

//

// Generate acknowledge -- just delay stb signal

// Generate acknowledge -- just delay stb signal

//

//

always @(posedge clk or posedge rst) begin

always @(posedge clk or `OR1200_RST_EVENT rst) begin

        if (rst) begin

        if (rst == `OR1200_RST_VALUE) begin

                dbg_ack   <=  1'b0;

                dbg_ack   <=  1'b0;

                dbg_ack_o <=  1'b0;

                dbg_ack_o <=  1'b0;

end

end

        else begin

        else begin

                dbg_ack   <=  dbg_stb_i;                // valid when du_dat_i

                dbg_ack   <=  dbg_stb_i;                // valid when du_dat_i

Line 584...

assign dbg_bp_o = dbg_bp_r;

assign dbg_bp_o = dbg_bp_r;

//

//

// Breakpoint activation register

// Breakpoint activation register

//

//

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dbg_bp_r <=  1'b0;

                dbg_bp_r <=  1'b0;

        else if (!ex_freeze)

        else if (!ex_freeze)

                dbg_bp_r <=  |except_stop

                dbg_bp_r <=  |except_stop

`ifdef OR1200_DU_DMR1_ST

`ifdef OR1200_DU_DMR1_ST

                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]

                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]

Line 603...

//

//

// Write to DMR1

// Write to DMR1

//

//

`ifdef OR1200_DU_DMR1

`ifdef OR1200_DU_DMR1

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dmr1 <= 25'h000_0000;

                dmr1 <= 25'h000_0000;

        else if (dmr1_sel && spr_write)

        else if (dmr1_sel && spr_write)

`ifdef OR1200_DU_HWBKPTS

`ifdef OR1200_DU_HWBKPTS

                dmr1 <=  spr_dat_i[24:0];

                dmr1 <=  spr_dat_i[24:0];

`else

`else

Line 620...

//

//

// Write to DMR2

// Write to DMR2

//

//

`ifdef OR1200_DU_DMR2

`ifdef OR1200_DU_DMR2

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dmr2 <= 24'h00_0000;

                dmr2 <= 24'h00_0000;

        else if (dmr2_sel && spr_write)

        else if (dmr2_sel && spr_write)

                dmr2 <=  spr_dat_i[23:0];

                dmr2 <=  spr_dat_i[23:0];

`else

`else

assign dmr2 = 24'h00_0000;

assign dmr2 = 24'h00_0000;

Line 633...

//

//

// Write to DSR

// Write to DSR

//

//

`ifdef OR1200_DU_DSR

`ifdef OR1200_DU_DSR

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};

                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};

        else if (dsr_sel && spr_write)

        else if (dsr_sel && spr_write)

                dsr <=  spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];

                dsr <=  spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];

`else

`else

assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};

assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};

Line 646...

//

//

// Write to DRR

// Write to DRR

//

//

`ifdef OR1200_DU_DRR

`ifdef OR1200_DU_DRR

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                drr <= 14'b0;

                drr <= 14'b0;

        else if (drr_sel && spr_write)

        else if (drr_sel && spr_write)

                drr <=  spr_dat_i[13:0];

                drr <=  spr_dat_i[13:0];

        else

        else

                drr <=  drr | except_stop;

                drr <=  drr | except_stop;

Line 661...

//

//

// Write to DVR0

// Write to DVR0

//

//

`ifdef OR1200_DU_DVR0

`ifdef OR1200_DU_DVR0

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dvr0 <= 32'h0000_0000;

                dvr0 <= 32'h0000_0000;

        else if (dvr0_sel && spr_write)

        else if (dvr0_sel && spr_write)

                dvr0 <=  spr_dat_i[31:0];

                dvr0 <=  spr_dat_i[31:0];

`else

`else

assign dvr0 = 32'h0000_0000;

assign dvr0 = 32'h0000_0000;

Line 674...

//

//

// Write to DVR1

// Write to DVR1

//

//

`ifdef OR1200_DU_DVR1

`ifdef OR1200_DU_DVR1

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dvr1 <= 32'h0000_0000;

                dvr1 <= 32'h0000_0000;

        else if (dvr1_sel && spr_write)

        else if (dvr1_sel && spr_write)

                dvr1 <=  spr_dat_i[31:0];

                dvr1 <=  spr_dat_i[31:0];

`else

`else

assign dvr1 = 32'h0000_0000;

assign dvr1 = 32'h0000_0000;

Line 687...

//

//

// Write to DVR2

// Write to DVR2

//

//

`ifdef OR1200_DU_DVR2

`ifdef OR1200_DU_DVR2

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dvr2 <= 32'h0000_0000;

                dvr2 <= 32'h0000_0000;

        else if (dvr2_sel && spr_write)

        else if (dvr2_sel && spr_write)

                dvr2 <=  spr_dat_i[31:0];

                dvr2 <=  spr_dat_i[31:0];

`else

`else

assign dvr2 = 32'h0000_0000;

assign dvr2 = 32'h0000_0000;

Line 700...

//

//

// Write to DVR3

// Write to DVR3

//

//

`ifdef OR1200_DU_DVR3

`ifdef OR1200_DU_DVR3

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dvr3 <= 32'h0000_0000;

                dvr3 <= 32'h0000_0000;

        else if (dvr3_sel && spr_write)

        else if (dvr3_sel && spr_write)

                dvr3 <=  spr_dat_i[31:0];

                dvr3 <=  spr_dat_i[31:0];

`else

`else

assign dvr3 = 32'h0000_0000;

assign dvr3 = 32'h0000_0000;

Line 713...

//

//

// Write to DVR4

// Write to DVR4

//

//

`ifdef OR1200_DU_DVR4

`ifdef OR1200_DU_DVR4

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dvr4 <= 32'h0000_0000;

                dvr4 <= 32'h0000_0000;

        else if (dvr4_sel && spr_write)

        else if (dvr4_sel && spr_write)

                dvr4 <=  spr_dat_i[31:0];

                dvr4 <=  spr_dat_i[31:0];

`else

`else

assign dvr4 = 32'h0000_0000;

assign dvr4 = 32'h0000_0000;

Line 726...

//

//

// Write to DVR5

// Write to DVR5

//

//

`ifdef OR1200_DU_DVR5

`ifdef OR1200_DU_DVR5

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dvr5 <= 32'h0000_0000;

                dvr5 <= 32'h0000_0000;

        else if (dvr5_sel && spr_write)

        else if (dvr5_sel && spr_write)

                dvr5 <=  spr_dat_i[31:0];

                dvr5 <=  spr_dat_i[31:0];

`else

`else

assign dvr5 = 32'h0000_0000;

assign dvr5 = 32'h0000_0000;

Line 739...

//

//

// Write to DVR6

// Write to DVR6

//

//

`ifdef OR1200_DU_DVR6

`ifdef OR1200_DU_DVR6

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dvr6 <= 32'h0000_0000;

                dvr6 <= 32'h0000_0000;

        else if (dvr6_sel && spr_write)

        else if (dvr6_sel && spr_write)

                dvr6 <=  spr_dat_i[31:0];

                dvr6 <=  spr_dat_i[31:0];

`else

`else

assign dvr6 = 32'h0000_0000;

assign dvr6 = 32'h0000_0000;

Line 752...

//

//

// Write to DVR7

// Write to DVR7

//

//

`ifdef OR1200_DU_DVR7

`ifdef OR1200_DU_DVR7

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dvr7 <= 32'h0000_0000;

                dvr7 <= 32'h0000_0000;

        else if (dvr7_sel && spr_write)

        else if (dvr7_sel && spr_write)

                dvr7 <=  spr_dat_i[31:0];

                dvr7 <=  spr_dat_i[31:0];

`else

`else

assign dvr7 = 32'h0000_0000;

assign dvr7 = 32'h0000_0000;

Line 765...

//

//

// Write to DCR0

// Write to DCR0

//

//

`ifdef OR1200_DU_DCR0

`ifdef OR1200_DU_DCR0

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dcr0 <= 8'h00;

                dcr0 <= 8'h00;

        else if (dcr0_sel && spr_write)

        else if (dcr0_sel && spr_write)

                dcr0 <=  spr_dat_i[7:0];

                dcr0 <=  spr_dat_i[7:0];

`else

`else

assign dcr0 = 8'h00;

assign dcr0 = 8'h00;

Line 778...

//

//

// Write to DCR1

// Write to DCR1

//

//

`ifdef OR1200_DU_DCR1

`ifdef OR1200_DU_DCR1

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dcr1 <= 8'h00;

                dcr1 <= 8'h00;

        else if (dcr1_sel && spr_write)

        else if (dcr1_sel && spr_write)

                dcr1 <=  spr_dat_i[7:0];

                dcr1 <=  spr_dat_i[7:0];

`else

`else

assign dcr1 = 8'h00;

assign dcr1 = 8'h00;

Line 791...

//

//

// Write to DCR2

// Write to DCR2

//

//

`ifdef OR1200_DU_DCR2

`ifdef OR1200_DU_DCR2

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dcr2 <= 8'h00;

                dcr2 <= 8'h00;

        else if (dcr2_sel && spr_write)

        else if (dcr2_sel && spr_write)

                dcr2 <=  spr_dat_i[7:0];

                dcr2 <=  spr_dat_i[7:0];

`else

`else

assign dcr2 = 8'h00;

assign dcr2 = 8'h00;

Line 804...

//

//

// Write to DCR3

// Write to DCR3

//

//

`ifdef OR1200_DU_DCR3

`ifdef OR1200_DU_DCR3

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dcr3 <= 8'h00;

                dcr3 <= 8'h00;

        else if (dcr3_sel && spr_write)

        else if (dcr3_sel && spr_write)

                dcr3 <=  spr_dat_i[7:0];

                dcr3 <=  spr_dat_i[7:0];

`else

`else

assign dcr3 = 8'h00;

assign dcr3 = 8'h00;

Line 817...

//

//

// Write to DCR4

// Write to DCR4

//

//

`ifdef OR1200_DU_DCR4

`ifdef OR1200_DU_DCR4

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dcr4 <= 8'h00;

                dcr4 <= 8'h00;

        else if (dcr4_sel && spr_write)

        else if (dcr4_sel && spr_write)

                dcr4 <=  spr_dat_i[7:0];

                dcr4 <=  spr_dat_i[7:0];

`else

`else

assign dcr4 = 8'h00;

assign dcr4 = 8'h00;

Line 830...

//

//

// Write to DCR5

// Write to DCR5

//

//

`ifdef OR1200_DU_DCR5

`ifdef OR1200_DU_DCR5

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dcr5 <= 8'h00;

                dcr5 <= 8'h00;

        else if (dcr5_sel && spr_write)

        else if (dcr5_sel && spr_write)

                dcr5 <=  spr_dat_i[7:0];

                dcr5 <=  spr_dat_i[7:0];

`else

`else

assign dcr5 = 8'h00;

assign dcr5 = 8'h00;

Line 843...

//

//

// Write to DCR6

// Write to DCR6

//

//

`ifdef OR1200_DU_DCR6

`ifdef OR1200_DU_DCR6

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dcr6 <= 8'h00;

                dcr6 <= 8'h00;

        else if (dcr6_sel && spr_write)

        else if (dcr6_sel && spr_write)

                dcr6 <=  spr_dat_i[7:0];

                dcr6 <=  spr_dat_i[7:0];

`else

`else

assign dcr6 = 8'h00;

assign dcr6 = 8'h00;

Line 856...

//

//

// Write to DCR7

// Write to DCR7

//

//

`ifdef OR1200_DU_DCR7

`ifdef OR1200_DU_DCR7

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dcr7 <= 8'h00;

                dcr7 <= 8'h00;

        else if (dcr7_sel && spr_write)

        else if (dcr7_sel && spr_write)

                dcr7 <=  spr_dat_i[7:0];

                dcr7 <=  spr_dat_i[7:0];

`else

`else

assign dcr7 = 8'h00;

assign dcr7 = 8'h00;

Line 869...

//

//

// Write to DWCR0

// Write to DWCR0

//

//

`ifdef OR1200_DU_DWCR0

`ifdef OR1200_DU_DWCR0

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dwcr0 <= 32'h0000_0000;

                dwcr0 <= 32'h0000_0000;

        else if (dwcr0_sel && spr_write)

        else if (dwcr0_sel && spr_write)

                dwcr0 <=  spr_dat_i[31:0];

                dwcr0 <=  spr_dat_i[31:0];

        else if (incr_wpcntr0)

        else if (incr_wpcntr0)

                dwcr0[`OR1200_DU_DWCR_COUNT] <=  dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;

                dwcr0[`OR1200_DU_DWCR_COUNT] <=  dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;

Line 884...

//

//

// Write to DWCR1

// Write to DWCR1

//

//

`ifdef OR1200_DU_DWCR1

`ifdef OR1200_DU_DWCR1

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                dwcr1 <= 32'h0000_0000;

                dwcr1 <= 32'h0000_0000;

        else if (dwcr1_sel && spr_write)

        else if (dwcr1_sel && spr_write)

                dwcr1 <=  spr_dat_i[31:0];

                dwcr1 <=  spr_dat_i[31:0];

        else if (incr_wpcntr1)

        else if (incr_wpcntr1)

                dwcr1[`OR1200_DU_DWCR_COUNT] <=  dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;

                dwcr1[`OR1200_DU_DWCR_COUNT] <=  dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;

Line 1618...

`else

`else

assign du_hwbkpt = 1'b0;

assign du_hwbkpt = 1'b0;

`endif

`endif

// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception

// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                du_hwbkpt_hold <=  1'b0;

                du_hwbkpt_hold <=  1'b0;

        else if (du_hwbkpt & ex_freeze)

        else if (du_hwbkpt & ex_freeze)

                du_hwbkpt_hold <=  1'b1;

                du_hwbkpt_hold <=  1'b1;

        else if (!ex_freeze)

        else if (!ex_freeze)

                du_hwbkpt_hold <=  1'b0;

                du_hwbkpt_hold <=  1'b0;

Line 1643...

assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);

assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);

//

//

// Trace buffer write address pointer

// Trace buffer write address pointer

//

//

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                tb_wadr <=  8'h00;

                tb_wadr <=  8'h00;

        else if (tb_enw)

        else if (tb_enw)

                tb_wadr <=  tb_wadr + 8'd1;

                tb_wadr <=  tb_wadr + 8'd1;

//

//

// Free running counter (time stamp)

// Free running counter (time stamp)

//

//

always @(posedge clk or posedge rst)

always @(posedge clk or `OR1200_RST_EVENT rst)

        if (rst)

        if (rst == `OR1200_RST_VALUE)

                tb_timstmp <=  32'h00000000;

                tb_timstmp <=  32'h00000000;

        else if (!dbg_bp_r)

        else if (!dbg_bp_r)

                tb_timstmp <=  tb_timstmp + 32'd1;

                tb_timstmp <=  tb_timstmp + 32'd1;

//

//

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_du.v] - Diff between revs 258 and 358