| Line 41... |
Line 41... |
//// ////
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//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//
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//
|
// CVS Revision History
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// CVS Revision History
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//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: or1200_du.v,v $
|
|
// Revision 2.0 2010/06/30 11:00:00 ORSoC
|
|
// Minor update:
|
|
// Bugs fixed.
|
|
//
|
|
// Revision 1.12 2005/10/19 11:37:56 jcastillo
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|
// Added support for RAMB16 Xilinx4/Spartan3 primitives
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|
//
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// Revision 1.11 2005/01/07 09:35:08 andreje
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// Revision 1.11 2005/01/07 09:35:08 andreje
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// du_hwbkpt disabled when debug unit not implemented
|
// du_hwbkpt disabled when debug unit not implemented
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//
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//
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// Revision 1.10 2004/04/05 08:29:57 lampret
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// Revision 1.10 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
|
// Merged branch_qmem into main tree.
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| Line 126... |
Line 133... |
clk, rst,
|
clk, rst,
|
dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
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dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
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dcpu_dat_dc, icpu_cycstb_i,
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dcpu_dat_dc, icpu_cycstb_i,
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ex_freeze, branch_op, ex_insn, id_pc,
|
ex_freeze, branch_op, ex_insn, id_pc,
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spr_dat_npc, rf_dataw,
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spr_dat_npc, rf_dataw,
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du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,
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du_dsr, du_dmr1, du_stall, du_addr, du_dat_i, du_dat_o,
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du_read, du_write, du_except, du_hwbkpt,
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du_read, du_write, du_except_stop, du_hwbkpt,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
|
|
|
// External Debug Interface
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// External Debug Interface
|
dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
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dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
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dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
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dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
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| Line 160... |
Line 167... |
input [dw-1:0] ex_insn; // EX insn
|
input [dw-1:0] ex_insn; // EX insn
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input [31:0] id_pc; // insn fetch EA
|
input [31:0] id_pc; // insn fetch EA
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input [31:0] spr_dat_npc; // Next PC (for trace)
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input [31:0] spr_dat_npc; // Next PC (for trace)
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input [31:0] rf_dataw; // ALU result (for trace)
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input [31:0] rf_dataw; // ALU result (for trace)
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output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
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output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
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output [24: 0] du_dmr1;
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output du_stall; // Debug Unit Stall
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output du_stall; // Debug Unit Stall
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output [aw-1:0] du_addr; // Debug Unit Address
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output [aw-1:0] du_addr; // Debug Unit Address
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input [dw-1:0] du_dat_i; // Debug Unit Data In
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input [dw-1:0] du_dat_i; // Debug Unit Data In
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output [dw-1:0] du_dat_o; // Debug Unit Data Out
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output [dw-1:0] du_dat_o; // Debug Unit Data Out
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output du_read; // Debug Unit Read Enable
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output du_read; // Debug Unit Read Enable
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output du_write; // Debug Unit Write Enable
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output du_write; // Debug Unit Write Enable
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input [12:0] du_except; // Exception masked by DSR
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input [12:0] du_except_stop; // Exception masked by DSR
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output du_hwbkpt; // Cause trap exception (HW Breakpoints)
|
output du_hwbkpt; // Cause trap exception (HW Breakpoints)
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input spr_cs; // SPR Chip Select
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input spr_cs; // SPR Chip Select
|
input spr_write; // SPR Read/Write
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input spr_write; // SPR Read/Write
|
input [aw-1:0] spr_addr; // SPR Address
|
input [aw-1:0] spr_addr; // SPR Address
|
input [dw-1:0] spr_dat_i; // SPR Data Input
|
input [dw-1:0] spr_dat_i; // SPR Data Input
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| Line 189... |
Line 197... |
input dbg_we_i; // External Write Enable
|
input dbg_we_i; // External Write Enable
|
input [aw-1:0] dbg_adr_i; // External Address Input
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input [aw-1:0] dbg_adr_i; // External Address Input
|
input [dw-1:0] dbg_dat_i; // External Data Input
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input [dw-1:0] dbg_dat_i; // External Data Input
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output [dw-1:0] dbg_dat_o; // External Data Output
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output [dw-1:0] dbg_dat_o; // External Data Output
|
output dbg_ack_o; // External Data Acknowledge (not WB compatible)
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output dbg_ack_o; // External Data Acknowledge (not WB compatible)
|
|
reg [dw-1:0] dbg_dat_o; // External Data Output
|
|
reg dbg_ack_o; // External Data Acknowledge (not WB compatible)
|
|
|
|
|
//
|
//
|
// Some connections go directly from the CPU through DU to Debug I/F
|
// Some connections go directly from the CPU through DU to Debug I/F
|
//
|
//
|
| Line 204... |
Line 214... |
// Show insn activity (temp, must be removed)
|
// Show insn activity (temp, must be removed)
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dbg_is_o <= #1 2'b00;
|
dbg_is_o <= #1 2'b00;
|
else if (!ex_freeze &
|
else if (!ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
|
~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
|
|
dbg_is_o <= #1 ~dbg_is_o;
|
dbg_is_o <= #1 ~dbg_is_o;
|
`ifdef UNUSED
|
`ifdef UNUSED
|
assign dbg_is_o = 2'b00;
|
assign dbg_is_o = 2'b00;
|
`endif
|
`endif
|
`else
|
`else
|
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
|
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
|
assign dbg_is_o = {1'b0, icpu_cycstb_i};
|
assign dbg_is_o = {1'b0, icpu_cycstb_i};
|
`endif
|
`endif
|
assign dbg_wp_o = 11'b000_0000_0000;
|
assign dbg_wp_o = 11'b000_0000_0000;
|
assign dbg_dat_o = du_dat_i;
|
|
|
|
//
|
//
|
// Some connections go directly from Debug I/F through DU to the CPU
|
// Some connections go directly from Debug I/F through DU to the CPU
|
//
|
//
|
assign du_stall = dbg_stall_i;
|
assign du_stall = dbg_stall_i;
|
assign du_addr = dbg_adr_i;
|
assign du_addr = dbg_adr_i;
|
assign du_dat_o = dbg_dat_i;
|
assign du_dat_o = dbg_dat_i;
|
assign du_read = dbg_stb_i && !dbg_we_i;
|
assign du_read = dbg_stb_i && !dbg_we_i;
|
assign du_write = dbg_stb_i && dbg_we_i;
|
assign du_write = dbg_stb_i && dbg_we_i;
|
|
|
|
reg dbg_ack;
|
//
|
//
|
// Generate acknowledge -- just delay stb signal
|
// Generate acknowledge -- just delay stb signal
|
//
|
//
|
reg dbg_ack_o;
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst)
|
if (rst) begin
|
if (rst)
|
dbg_ack <= #1 1'b0;
|
dbg_ack_o <= #1 1'b0;
|
dbg_ack_o <= #1 1'b0;
|
else
|
end
|
dbg_ack_o <= #1 dbg_stb_i;
|
else begin
|
|
dbg_ack <= #1 dbg_stb_i; // valid when du_dat_i
|
|
dbg_ack_o <= #1 dbg_ack & dbg_stb_i; // valid when dbg_dat_o
|
|
end
|
|
end
|
|
|
|
//
|
|
// Register data output
|
|
//
|
|
always @(posedge clk)
|
|
dbg_dat_o <= #1 du_dat_i;
|
|
|
`ifdef OR1200_DU_IMPLEMENTED
|
`ifdef OR1200_DU_IMPLEMENTED
|
|
|
//
|
//
|
// Debug Mode Register 1
|
// Debug Mode Register 1
|
| Line 246... |
Line 265... |
`ifdef OR1200_DU_DMR1
|
`ifdef OR1200_DU_DMR1
|
reg [24:0] dmr1; // DMR1 implemented
|
reg [24:0] dmr1; // DMR1 implemented
|
`else
|
`else
|
wire [24:0] dmr1; // DMR1 not implemented
|
wire [24:0] dmr1; // DMR1 not implemented
|
`endif
|
`endif
|
|
assign du_dmr1 = dmr1;
|
|
|
//
|
//
|
// Debug Mode Register 2
|
// Debug Mode Register 2
|
//
|
//
|
`ifdef OR1200_DU_DMR2
|
`ifdef OR1200_DU_DMR2
|
| Line 494... |
Line 514... |
reg incr_wpcntr0;
|
reg incr_wpcntr0;
|
reg incr_wpcntr1;
|
reg incr_wpcntr1;
|
reg [10:0] wp;
|
reg [10:0] wp;
|
`endif
|
`endif
|
wire du_hwbkpt;
|
wire du_hwbkpt;
|
|
reg du_hwbkpt_hold;
|
`ifdef OR1200_DU_READREGS
|
`ifdef OR1200_DU_READREGS
|
reg [31:0] spr_dat_o;
|
reg [31:0] spr_dat_o;
|
`endif
|
`endif
|
reg [13:0] except_stop; // Exceptions that stop because of DSR
|
reg [13:0] except_stop; // Exceptions that stop because of DSR
|
`ifdef OR1200_DU_TB_IMPLEMENTED
|
`ifdef OR1200_DU_TB_IMPLEMENTED
|
| Line 581... |
Line 602... |
`endif
|
`endif
|
|
|
//
|
//
|
// Decode started exception
|
// Decode started exception
|
//
|
//
|
always @(du_except) begin
|
always @(du_except_stop) begin
|
except_stop = 14'b0000_0000_0000;
|
except_stop = 14'b0000_0000_0000;
|
casex (du_except)
|
casex (du_except_stop)
|
13'b1_xxxx_xxxx_xxxx:
|
13'b1_xxxx_xxxx_xxxx: begin
|
except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
|
|
end
|
13'b0_1xxx_xxxx_xxxx: begin
|
13'b0_1xxx_xxxx_xxxx: begin
|
except_stop[`OR1200_DU_DRR_IE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_IE] = 1'b1;
|
end
|
end
|
13'b0_01xx_xxxx_xxxx: begin
|
13'b0_01xx_xxxx_xxxx: begin
|
except_stop[`OR1200_DU_DRR_IME] = 1'b1;
|
except_stop[`OR1200_DU_DRR_IME] = 1'b1;
|
end
|
end
|
13'b0_001x_xxxx_xxxx:
|
13'b0_001x_xxxx_xxxx: begin
|
except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
|
|
end
|
13'b0_0001_xxxx_xxxx: begin
|
13'b0_0001_xxxx_xxxx: begin
|
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
|
end
|
end
|
13'b0_0000_1xxx_xxxx:
|
13'b0_0000_1xxx_xxxx: begin
|
except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
|
|
end
|
13'b0_0000_01xx_xxxx: begin
|
13'b0_0000_01xx_xxxx: begin
|
except_stop[`OR1200_DU_DRR_AE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_AE] = 1'b1;
|
end
|
end
|
13'b0_0000_001x_xxxx: begin
|
13'b0_0000_001x_xxxx: begin
|
except_stop[`OR1200_DU_DRR_DME] = 1'b1;
|
except_stop[`OR1200_DU_DRR_DME] = 1'b1;
|
end
|
end
|
13'b0_0000_0001_xxxx:
|
13'b0_0000_0001_xxxx: begin
|
except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
|
13'b0_0000_0000_1xxx:
|
end
|
|
13'b0_0000_0000_1xxx: begin
|
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
|
|
end
|
13'b0_0000_0000_01xx: begin
|
13'b0_0000_0000_01xx: begin
|
except_stop[`OR1200_DU_DRR_RE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_RE] = 1'b1;
|
end
|
end
|
13'b0_0000_0000_001x: begin
|
13'b0_0000_0000_001x: begin
|
except_stop[`OR1200_DU_DRR_TE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_TE] = 1'b1;
|
end
|
end
|
13'b0_0000_0000_0001:
|
13'b0_0000_0000_0001: begin
|
except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
|
except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
|
|
end
|
default:
|
default:
|
except_stop = 14'b0000_0000_0000;
|
except_stop = 14'b0000_0000_0000;
|
endcase
|
endcase
|
end
|
end
|
|
|
| Line 639... |
Line 666... |
dbg_bp_r <= #1 |except_stop
|
dbg_bp_r <= #1 |except_stop
|
`ifdef OR1200_DU_DMR1_ST
|
`ifdef OR1200_DU_DMR1_ST
|
| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
|
| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
|
`endif
|
`endif
|
`ifdef OR1200_DU_DMR1_BT
|
`ifdef OR1200_DU_DMR1_BT
|
| (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
|
| (branch_op != `OR1200_BRANCHOP_NOP) & (branch_op != `OR1200_BRANCHOP_RFE) & dmr1[`OR1200_DU_DMR1_BT]
|
`endif
|
`endif
|
;
|
;
|
else
|
else
|
dbg_bp_r <= #1 |except_stop;
|
dbg_bp_r <= #1 |except_stop;
|
|
|
| Line 1103... |
Line 1130... |
casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]})
|
casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]})
|
4'b0_xxx,
|
4'b0_xxx,
|
4'b1_000,
|
4'b1_000,
|
4'b1_111: match0 = 1'b0;
|
4'b1_111: match0 = 1'b0;
|
4'b1_001: match0 =
|
4'b1_001: match0 =
|
((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) ==
|
({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} ==
|
(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
|
{(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
|
4'b1_010: match0 =
|
4'b1_010: match0 =
|
((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <
|
({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <
|
(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
|
{(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
|
4'b1_011: match0 =
|
4'b1_011: match0 =
|
((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <=
|
({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <=
|
(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
|
{(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
|
4'b1_100: match0 =
|
4'b1_100: match0 =
|
((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >
|
({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >
|
(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
|
{(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
|
4'b1_101: match0 =
|
4'b1_101: match0 =
|
((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >=
|
({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >=
|
(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
|
{(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
|
4'b1_110: match0 =
|
4'b1_110: match0 =
|
((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) !=
|
({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} !=
|
(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
|
{(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
|
endcase
|
endcase
|
|
|
//
|
//
|
// Watchpoint 0
|
// Watchpoint 0
|
//
|
//
|
| Line 1167... |
Line 1194... |
casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]})
|
casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]})
|
4'b0_xxx,
|
4'b0_xxx,
|
4'b1_000,
|
4'b1_000,
|
4'b1_111: match1 = 1'b0;
|
4'b1_111: match1 = 1'b0;
|
4'b1_001: match1 =
|
4'b1_001: match1 =
|
((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) ==
|
({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} ==
|
(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
|
{(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
|
4'b1_010: match1 =
|
4'b1_010: match1 =
|
((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <
|
({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <
|
(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
|
{(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
|
4'b1_011: match1 =
|
4'b1_011: match1 =
|
((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <=
|
({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <=
|
(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
|
{(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
|
4'b1_100: match1 =
|
4'b1_100: match1 =
|
((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >
|
({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >
|
(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
|
{(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
|
4'b1_101: match1 =
|
4'b1_101: match1 =
|
((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >=
|
({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >=
|
(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
|
{(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
|
4'b1_110: match1 =
|
4'b1_110: match1 =
|
((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) !=
|
({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} !=
|
(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
|
{(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
|
endcase
|
endcase
|
|
|
//
|
//
|
// Watchpoint 1
|
// Watchpoint 1
|
//
|
//
|
| Line 1231... |
Line 1258... |
casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]})
|
casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]})
|
4'b0_xxx,
|
4'b0_xxx,
|
4'b1_000,
|
4'b1_000,
|
4'b1_111: match2 = 1'b0;
|
4'b1_111: match2 = 1'b0;
|
4'b1_001: match2 =
|
4'b1_001: match2 =
|
((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) ==
|
({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} ==
|
(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
|
{(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
|
4'b1_010: match2 =
|
4'b1_010: match2 =
|
((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <
|
({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <
|
(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
|
{(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
|
4'b1_011: match2 =
|
4'b1_011: match2 =
|
((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <=
|
({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <=
|
(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
|
{(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
|
4'b1_100: match2 =
|
4'b1_100: match2 =
|
((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >
|
({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >
|
(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
|
{(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
|
4'b1_101: match2 =
|
4'b1_101: match2 =
|
((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >=
|
({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >=
|
(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
|
{(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
|
4'b1_110: match2 =
|
4'b1_110: match2 =
|
((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) !=
|
({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} !=
|
(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
|
{(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
|
endcase
|
endcase
|
|
|
//
|
//
|
// Watchpoint 2
|
// Watchpoint 2
|
//
|
//
|
| Line 1295... |
Line 1322... |
casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]})
|
casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]})
|
4'b0_xxx,
|
4'b0_xxx,
|
4'b1_000,
|
4'b1_000,
|
4'b1_111: match3 = 1'b0;
|
4'b1_111: match3 = 1'b0;
|
4'b1_001: match3 =
|
4'b1_001: match3 =
|
((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) ==
|
({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} ==
|
(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
|
{(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
|
4'b1_010: match3 =
|
4'b1_010: match3 =
|
((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <
|
({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <
|
(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
|
{(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
|
4'b1_011: match3 =
|
4'b1_011: match3 =
|
((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <=
|
({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <=
|
(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
|
{(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
|
4'b1_100: match3 =
|
4'b1_100: match3 =
|
((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >
|
({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >
|
(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
|
{(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
|
4'b1_101: match3 =
|
4'b1_101: match3 =
|
((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >=
|
({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >=
|
(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
|
{(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
|
4'b1_110: match3 =
|
4'b1_110: match3 =
|
((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) !=
|
({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} !=
|
(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
|
{(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
|
endcase
|
endcase
|
|
|
//
|
//
|
// Watchpoint 3
|
// Watchpoint 3
|
//
|
//
|
| Line 1359... |
Line 1386... |
casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]})
|
casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]})
|
4'b0_xxx,
|
4'b0_xxx,
|
4'b1_000,
|
4'b1_000,
|
4'b1_111: match4 = 1'b0;
|
4'b1_111: match4 = 1'b0;
|
4'b1_001: match4 =
|
4'b1_001: match4 =
|
((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) ==
|
({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} ==
|
(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
|
{(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
|
4'b1_010: match4 =
|
4'b1_010: match4 =
|
((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <
|
({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <
|
(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
|
{(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
|
4'b1_011: match4 =
|
4'b1_011: match4 =
|
((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <=
|
({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <=
|
(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
|
{(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
|
4'b1_100: match4 =
|
4'b1_100: match4 =
|
((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >
|
({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >
|
(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
|
{(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
|
4'b1_101: match4 =
|
4'b1_101: match4 =
|
((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >=
|
({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >=
|
(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
|
{(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
|
4'b1_110: match4 =
|
4'b1_110: match4 =
|
((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) !=
|
({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} !=
|
(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
|
{(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
|
endcase
|
endcase
|
|
|
//
|
//
|
// Watchpoint 4
|
// Watchpoint 4
|
//
|
//
|
| Line 1423... |
Line 1450... |
casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]})
|
casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]})
|
4'b0_xxx,
|
4'b0_xxx,
|
4'b1_000,
|
4'b1_000,
|
4'b1_111: match5 = 1'b0;
|
4'b1_111: match5 = 1'b0;
|
4'b1_001: match5 =
|
4'b1_001: match5 =
|
((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) ==
|
({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} ==
|
(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
|
{(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
|
4'b1_010: match5 =
|
4'b1_010: match5 =
|
((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <
|
({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <
|
(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
|
{(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
|
4'b1_011: match5 =
|
4'b1_011: match5 =
|
((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <=
|
({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <=
|
(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
|
{(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
|
4'b1_100: match5 =
|
4'b1_100: match5 =
|
((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >
|
({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >
|
(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
|
{(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
|
4'b1_101: match5 =
|
4'b1_101: match5 =
|
((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >=
|
({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >=
|
(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
|
{(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
|
4'b1_110: match5 =
|
4'b1_110: match5 =
|
((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) !=
|
({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} !=
|
(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
|
{(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
|
endcase
|
endcase
|
|
|
//
|
//
|
// Watchpoint 5
|
// Watchpoint 5
|
//
|
//
|
| Line 1487... |
Line 1514... |
casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]})
|
casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]})
|
4'b0_xxx,
|
4'b0_xxx,
|
4'b1_000,
|
4'b1_000,
|
4'b1_111: match6 = 1'b0;
|
4'b1_111: match6 = 1'b0;
|
4'b1_001: match6 =
|
4'b1_001: match6 =
|
((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) ==
|
({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} ==
|
(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
|
{(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
|
4'b1_010: match6 =
|
4'b1_010: match6 =
|
((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <
|
({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <
|
(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
|
{(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
|
4'b1_011: match6 =
|
4'b1_011: match6 =
|
((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <=
|
({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <=
|
(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
|
{(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
|
4'b1_100: match6 =
|
4'b1_100: match6 =
|
((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >
|
({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >
|
(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
|
{(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
|
4'b1_101: match6 =
|
4'b1_101: match6 =
|
((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >=
|
({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >=
|
(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
|
{(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
|
4'b1_110: match6 =
|
4'b1_110: match6 =
|
((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) !=
|
({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} !=
|
(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
|
{(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
|
endcase
|
endcase
|
|
|
//
|
//
|
// Watchpoint 6
|
// Watchpoint 6
|
//
|
//
|
| Line 1551... |
Line 1578... |
casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
|
casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
|
4'b0_xxx,
|
4'b0_xxx,
|
4'b1_000,
|
4'b1_000,
|
4'b1_111: match7 = 1'b0;
|
4'b1_111: match7 = 1'b0;
|
4'b1_001: match7 =
|
4'b1_001: match7 =
|
((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) ==
|
({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} ==
|
(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
|
{(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
|
4'b1_010: match7 =
|
4'b1_010: match7 =
|
((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <
|
({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <
|
(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
|
{(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
|
4'b1_011: match7 =
|
4'b1_011: match7 =
|
((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <=
|
({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <=
|
(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
|
{(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
|
4'b1_100: match7 =
|
4'b1_100: match7 =
|
((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >
|
({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >
|
(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
|
{(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
|
4'b1_101: match7 =
|
4'b1_101: match7 =
|
((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >=
|
({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >=
|
(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
|
{(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
|
4'b1_110: match7 =
|
4'b1_110: match7 =
|
((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) !=
|
({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} !=
|
(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
|
{(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
|
endcase
|
endcase
|
|
|
//
|
//
|
// Watchpoint 7
|
// Watchpoint 7
|
//
|
//
|
| Line 1658... |
Line 1685... |
|
|
//
|
//
|
// Watchpoints can cause trap exception
|
// Watchpoints can cause trap exception
|
//
|
//
|
`ifdef OR1200_DU_HWBKPTS
|
`ifdef OR1200_DU_HWBKPTS
|
assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]);
|
assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]) | du_hwbkpt_hold | (dbg_bp_r & ~dsr[`OR1200_DU_DSR_TE]);
|
`else
|
`else
|
assign du_hwbkpt = 1'b0;
|
assign du_hwbkpt = 1'b0;
|
`endif
|
`endif
|
|
|
|
// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception
|
|
always @(posedge clk or posedge rst)
|
|
if (rst)
|
|
du_hwbkpt_hold <= #1 1'b0;
|
|
else if (du_hwbkpt & ex_freeze)
|
|
du_hwbkpt_hold <= #1 1'b1;
|
|
else if (!ex_freeze)
|
|
du_hwbkpt_hold <= #1 1'b0;
|
|
|
`ifdef OR1200_DU_TB_IMPLEMENTED
|
`ifdef OR1200_DU_TB_IMPLEMENTED
|
//
|
//
|
// Simple trace buffer
|
// Simple trace buffer
|
// (right now hardcoded for Xilinx Virtex FPGAs)
|
// (right now hardcoded for Xilinx Virtex FPGAs)
|
//
|
//
|
| Line 1701... |
Line 1737... |
// Trace buffer RAMs
|
// Trace buffer RAMs
|
//
|
//
|
|
|
or1200_dpram_256x32 tbia_ram(
|
or1200_dpram_256x32 tbia_ram(
|
.clk_a(clk),
|
.clk_a(clk),
|
.rst_a(rst),
|
.rst_a(1'b0),
|
.addr_a(spr_addr[7:0]),
|
.addr_a(spr_addr[7:0]),
|
.ce_a(1'b1),
|
.ce_a(1'b1),
|
.oe_a(1'b1),
|
.oe_a(1'b1),
|
.do_a(tbia_dat_o),
|
.do_a(tbia_dat_o),
|
|
|
.clk_b(clk),
|
.clk_b(clk),
|
.rst_b(rst),
|
.rst_b(1'b0),
|
.addr_b(tb_wadr),
|
.addr_b(tb_wadr),
|
.di_b(spr_dat_npc),
|
.di_b(spr_dat_npc),
|
.ce_b(1'b1),
|
.ce_b(1'b1),
|
.we_b(tb_enw)
|
.we_b(tb_enw)
|
|
|
);
|
);
|
|
|
or1200_dpram_256x32 tbim_ram(
|
or1200_dpram_256x32 tbim_ram(
|
.clk_a(clk),
|
.clk_a(clk),
|
.rst_a(rst),
|
.rst_a(1'b0),
|
.addr_a(spr_addr[7:0]),
|
.addr_a(spr_addr[7:0]),
|
.ce_a(1'b1),
|
.ce_a(1'b1),
|
.oe_a(1'b1),
|
.oe_a(1'b1),
|
.do_a(tbim_dat_o),
|
.do_a(tbim_dat_o),
|
|
|
.clk_b(clk),
|
.clk_b(clk),
|
.rst_b(rst),
|
.rst_b(1'b0),
|
.addr_b(tb_wadr),
|
.addr_b(tb_wadr),
|
.di_b(ex_insn),
|
.di_b(ex_insn),
|
.ce_b(1'b1),
|
.ce_b(1'b1),
|
.we_b(tb_enw)
|
.we_b(tb_enw)
|
);
|
);
|
|
|
or1200_dpram_256x32 tbar_ram(
|
or1200_dpram_256x32 tbar_ram(
|
.clk_a(clk),
|
.clk_a(clk),
|
.rst_a(rst),
|
.rst_a(1'b0),
|
.addr_a(spr_addr[7:0]),
|
.addr_a(spr_addr[7:0]),
|
.ce_a(1'b1),
|
.ce_a(1'b1),
|
.oe_a(1'b1),
|
.oe_a(1'b1),
|
.do_a(tbar_dat_o),
|
.do_a(tbar_dat_o),
|
|
|
.clk_b(clk),
|
.clk_b(clk),
|
.rst_b(rst),
|
.rst_b(1'b0),
|
.addr_b(tb_wadr),
|
.addr_b(tb_wadr),
|
.di_b(rf_dataw),
|
.di_b(rf_dataw),
|
.ce_b(1'b1),
|
.ce_b(1'b1),
|
.we_b(tb_enw)
|
.we_b(tb_enw)
|
);
|
);
|
|
|
or1200_dpram_256x32 tbts_ram(
|
or1200_dpram_256x32 tbts_ram(
|
.clk_a(clk),
|
.clk_a(clk),
|
.rst_a(rst),
|
.rst_a(1'b0),
|
.addr_a(spr_addr[7:0]),
|
.addr_a(spr_addr[7:0]),
|
.ce_a(1'b1),
|
.ce_a(1'b1),
|
.oe_a(1'b1),
|
.oe_a(1'b1),
|
.do_a(tbts_dat_o),
|
.do_a(tbts_dat_o),
|
|
|
.clk_b(clk),
|
.clk_b(clk),
|
.rst_b(rst),
|
.rst_b(1'b0),
|
.addr_b(tb_wadr),
|
.addr_b(tb_wadr),
|
.di_b(tb_timstmp),
|
.di_b(tb_timstmp),
|
.ce_b(1'b1),
|
.ce_b(1'b1),
|
.we_b(tb_enw)
|
.we_b(tb_enw)
|
);
|
);
|
| Line 1780... |
Line 1816... |
//
|
//
|
// When DU is not implemented, drive all outputs as would when DU is disabled
|
// When DU is not implemented, drive all outputs as would when DU is disabled
|
//
|
//
|
assign dbg_bp_o = 1'b0;
|
assign dbg_bp_o = 1'b0;
|
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
|
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
|
|
assign du_dmr1 = {25{1'b0}};
|
assign du_hwbkpt = 1'b0;
|
assign du_hwbkpt = 1'b0;
|
|
|
//
|
//
|
// Read DU registers
|
// Read DU registers
|
//
|
//
|
