OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_du.v] - Diff between revs 185 and 258

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 185 Rev 258
Line 141... Line 141...
//
//
// Show insn activity (temp, must be removed)
// Show insn activity (temp, must be removed)
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dbg_is_o <= #1 2'b00;
                dbg_is_o <=  2'b00;
        else if (!ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
        else if (!ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
                dbg_is_o <= #1 ~dbg_is_o;
                dbg_is_o <=  ~dbg_is_o;
`ifdef UNUSED
`ifdef UNUSED
assign dbg_is_o = 2'b00;
assign dbg_is_o = 2'b00;
`endif
`endif
`else
`else
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
Line 168... Line 168...
//
//
// Generate acknowledge -- just delay stb signal
// Generate acknowledge -- just delay stb signal
//
//
always @(posedge clk or posedge rst) begin
always @(posedge clk or posedge rst) begin
        if (rst) begin
        if (rst) begin
                dbg_ack   <= #1 1'b0;
                dbg_ack   <=  1'b0;
                dbg_ack_o <= #1 1'b0;
                dbg_ack_o <=  1'b0;
        end
        end
        else begin
        else begin
                dbg_ack   <= #1 dbg_stb_i;              // valid when du_dat_i 
                dbg_ack   <=  dbg_stb_i;                // valid when du_dat_i 
                dbg_ack_o <= #1 dbg_ack & dbg_stb_i;    // valid when dbg_dat_o 
                dbg_ack_o <=  dbg_ack & dbg_stb_i;      // valid when dbg_dat_o 
        end
        end
end
end
 
 
// 
// 
// Register data output
// Register data output
//
//
always @(posedge clk)
always @(posedge clk)
    dbg_dat_o <= #1 du_dat_i;
    dbg_dat_o <=  du_dat_i;
 
 
`ifdef OR1200_DU_IMPLEMENTED
`ifdef OR1200_DU_IMPLEMENTED
 
 
//
//
// Debug Mode Register 1
// Debug Mode Register 1
Line 586... Line 586...
//
//
// Breakpoint activation register
// Breakpoint activation register
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dbg_bp_r <= #1 1'b0;
                dbg_bp_r <=  1'b0;
        else if (!ex_freeze)
        else if (!ex_freeze)
                dbg_bp_r <= #1 |except_stop
                dbg_bp_r <=  |except_stop
`ifdef OR1200_DU_DMR1_ST
`ifdef OR1200_DU_DMR1_ST
                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
`endif
`endif
`ifdef OR1200_DU_DMR1_BT
`ifdef OR1200_DU_DMR1_BT
                        | (branch_op != `OR1200_BRANCHOP_NOP) & (branch_op != `OR1200_BRANCHOP_RFE) & dmr1[`OR1200_DU_DMR1_BT]
                        | (branch_op != `OR1200_BRANCHOP_NOP) & (branch_op != `OR1200_BRANCHOP_RFE) & dmr1[`OR1200_DU_DMR1_BT]
`endif
`endif
                        ;
                        ;
        else
        else
                dbg_bp_r <= #1 |except_stop;
                dbg_bp_r <=  |except_stop;
 
 
//
//
// Write to DMR1
// Write to DMR1
//
//
`ifdef OR1200_DU_DMR1
`ifdef OR1200_DU_DMR1
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dmr1 <= 25'h000_0000;
                dmr1 <= 25'h000_0000;
        else if (dmr1_sel && spr_write)
        else if (dmr1_sel && spr_write)
`ifdef OR1200_DU_HWBKPTS
`ifdef OR1200_DU_HWBKPTS
                dmr1 <= #1 spr_dat_i[24:0];
                dmr1 <=  spr_dat_i[24:0];
`else
`else
                dmr1 <= #1 {1'b0, spr_dat_i[23:22], 22'h00_0000};
                dmr1 <=  {1'b0, spr_dat_i[23:22], 22'h00_0000};
`endif
`endif
`else
`else
assign dmr1 = 25'h000_0000;
assign dmr1 = 25'h000_0000;
`endif
`endif
 
 
Line 624... Line 624...
`ifdef OR1200_DU_DMR2
`ifdef OR1200_DU_DMR2
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dmr2 <= 24'h00_0000;
                dmr2 <= 24'h00_0000;
        else if (dmr2_sel && spr_write)
        else if (dmr2_sel && spr_write)
                dmr2 <= #1 spr_dat_i[23:0];
                dmr2 <=  spr_dat_i[23:0];
`else
`else
assign dmr2 = 24'h00_0000;
assign dmr2 = 24'h00_0000;
`endif
`endif
 
 
//
//
Line 637... Line 637...
`ifdef OR1200_DU_DSR
`ifdef OR1200_DU_DSR
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
        else if (dsr_sel && spr_write)
        else if (dsr_sel && spr_write)
                dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
                dsr <=  spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
`else
`else
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
`endif
`endif
 
 
//
//
Line 650... Line 650...
`ifdef OR1200_DU_DRR
`ifdef OR1200_DU_DRR
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                drr <= 14'b0;
                drr <= 14'b0;
        else if (drr_sel && spr_write)
        else if (drr_sel && spr_write)
                drr <= #1 spr_dat_i[13:0];
                drr <=  spr_dat_i[13:0];
        else
        else
                drr <= #1 drr | except_stop;
                drr <=  drr | except_stop;
`else
`else
assign drr = 14'b0;
assign drr = 14'b0;
`endif
`endif
 
 
//
//
Line 665... Line 665...
`ifdef OR1200_DU_DVR0
`ifdef OR1200_DU_DVR0
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dvr0 <= 32'h0000_0000;
                dvr0 <= 32'h0000_0000;
        else if (dvr0_sel && spr_write)
        else if (dvr0_sel && spr_write)
                dvr0 <= #1 spr_dat_i[31:0];
                dvr0 <=  spr_dat_i[31:0];
`else
`else
assign dvr0 = 32'h0000_0000;
assign dvr0 = 32'h0000_0000;
`endif
`endif
 
 
//
//
Line 678... Line 678...
`ifdef OR1200_DU_DVR1
`ifdef OR1200_DU_DVR1
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dvr1 <= 32'h0000_0000;
                dvr1 <= 32'h0000_0000;
        else if (dvr1_sel && spr_write)
        else if (dvr1_sel && spr_write)
                dvr1 <= #1 spr_dat_i[31:0];
                dvr1 <=  spr_dat_i[31:0];
`else
`else
assign dvr1 = 32'h0000_0000;
assign dvr1 = 32'h0000_0000;
`endif
`endif
 
 
//
//
Line 691... Line 691...
`ifdef OR1200_DU_DVR2
`ifdef OR1200_DU_DVR2
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dvr2 <= 32'h0000_0000;
                dvr2 <= 32'h0000_0000;
        else if (dvr2_sel && spr_write)
        else if (dvr2_sel && spr_write)
                dvr2 <= #1 spr_dat_i[31:0];
                dvr2 <=  spr_dat_i[31:0];
`else
`else
assign dvr2 = 32'h0000_0000;
assign dvr2 = 32'h0000_0000;
`endif
`endif
 
 
//
//
Line 704... Line 704...
`ifdef OR1200_DU_DVR3
`ifdef OR1200_DU_DVR3
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dvr3 <= 32'h0000_0000;
                dvr3 <= 32'h0000_0000;
        else if (dvr3_sel && spr_write)
        else if (dvr3_sel && spr_write)
                dvr3 <= #1 spr_dat_i[31:0];
                dvr3 <=  spr_dat_i[31:0];
`else
`else
assign dvr3 = 32'h0000_0000;
assign dvr3 = 32'h0000_0000;
`endif
`endif
 
 
//
//
Line 717... Line 717...
`ifdef OR1200_DU_DVR4
`ifdef OR1200_DU_DVR4
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dvr4 <= 32'h0000_0000;
                dvr4 <= 32'h0000_0000;
        else if (dvr4_sel && spr_write)
        else if (dvr4_sel && spr_write)
                dvr4 <= #1 spr_dat_i[31:0];
                dvr4 <=  spr_dat_i[31:0];
`else
`else
assign dvr4 = 32'h0000_0000;
assign dvr4 = 32'h0000_0000;
`endif
`endif
 
 
//
//
Line 730... Line 730...
`ifdef OR1200_DU_DVR5
`ifdef OR1200_DU_DVR5
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dvr5 <= 32'h0000_0000;
                dvr5 <= 32'h0000_0000;
        else if (dvr5_sel && spr_write)
        else if (dvr5_sel && spr_write)
                dvr5 <= #1 spr_dat_i[31:0];
                dvr5 <=  spr_dat_i[31:0];
`else
`else
assign dvr5 = 32'h0000_0000;
assign dvr5 = 32'h0000_0000;
`endif
`endif
 
 
//
//
Line 743... Line 743...
`ifdef OR1200_DU_DVR6
`ifdef OR1200_DU_DVR6
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dvr6 <= 32'h0000_0000;
                dvr6 <= 32'h0000_0000;
        else if (dvr6_sel && spr_write)
        else if (dvr6_sel && spr_write)
                dvr6 <= #1 spr_dat_i[31:0];
                dvr6 <=  spr_dat_i[31:0];
`else
`else
assign dvr6 = 32'h0000_0000;
assign dvr6 = 32'h0000_0000;
`endif
`endif
 
 
//
//
Line 756... Line 756...
`ifdef OR1200_DU_DVR7
`ifdef OR1200_DU_DVR7
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dvr7 <= 32'h0000_0000;
                dvr7 <= 32'h0000_0000;
        else if (dvr7_sel && spr_write)
        else if (dvr7_sel && spr_write)
                dvr7 <= #1 spr_dat_i[31:0];
                dvr7 <=  spr_dat_i[31:0];
`else
`else
assign dvr7 = 32'h0000_0000;
assign dvr7 = 32'h0000_0000;
`endif
`endif
 
 
//
//
Line 769... Line 769...
`ifdef OR1200_DU_DCR0
`ifdef OR1200_DU_DCR0
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dcr0 <= 8'h00;
                dcr0 <= 8'h00;
        else if (dcr0_sel && spr_write)
        else if (dcr0_sel && spr_write)
                dcr0 <= #1 spr_dat_i[7:0];
                dcr0 <=  spr_dat_i[7:0];
`else
`else
assign dcr0 = 8'h00;
assign dcr0 = 8'h00;
`endif
`endif
 
 
//
//
Line 782... Line 782...
`ifdef OR1200_DU_DCR1
`ifdef OR1200_DU_DCR1
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dcr1 <= 8'h00;
                dcr1 <= 8'h00;
        else if (dcr1_sel && spr_write)
        else if (dcr1_sel && spr_write)
                dcr1 <= #1 spr_dat_i[7:0];
                dcr1 <=  spr_dat_i[7:0];
`else
`else
assign dcr1 = 8'h00;
assign dcr1 = 8'h00;
`endif
`endif
 
 
//
//
Line 795... Line 795...
`ifdef OR1200_DU_DCR2
`ifdef OR1200_DU_DCR2
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dcr2 <= 8'h00;
                dcr2 <= 8'h00;
        else if (dcr2_sel && spr_write)
        else if (dcr2_sel && spr_write)
                dcr2 <= #1 spr_dat_i[7:0];
                dcr2 <=  spr_dat_i[7:0];
`else
`else
assign dcr2 = 8'h00;
assign dcr2 = 8'h00;
`endif
`endif
 
 
//
//
Line 808... Line 808...
`ifdef OR1200_DU_DCR3
`ifdef OR1200_DU_DCR3
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dcr3 <= 8'h00;
                dcr3 <= 8'h00;
        else if (dcr3_sel && spr_write)
        else if (dcr3_sel && spr_write)
                dcr3 <= #1 spr_dat_i[7:0];
                dcr3 <=  spr_dat_i[7:0];
`else
`else
assign dcr3 = 8'h00;
assign dcr3 = 8'h00;
`endif
`endif
 
 
//
//
Line 821... Line 821...
`ifdef OR1200_DU_DCR4
`ifdef OR1200_DU_DCR4
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dcr4 <= 8'h00;
                dcr4 <= 8'h00;
        else if (dcr4_sel && spr_write)
        else if (dcr4_sel && spr_write)
                dcr4 <= #1 spr_dat_i[7:0];
                dcr4 <=  spr_dat_i[7:0];
`else
`else
assign dcr4 = 8'h00;
assign dcr4 = 8'h00;
`endif
`endif
 
 
//
//
Line 834... Line 834...
`ifdef OR1200_DU_DCR5
`ifdef OR1200_DU_DCR5
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dcr5 <= 8'h00;
                dcr5 <= 8'h00;
        else if (dcr5_sel && spr_write)
        else if (dcr5_sel && spr_write)
                dcr5 <= #1 spr_dat_i[7:0];
                dcr5 <=  spr_dat_i[7:0];
`else
`else
assign dcr5 = 8'h00;
assign dcr5 = 8'h00;
`endif
`endif
 
 
//
//
Line 847... Line 847...
`ifdef OR1200_DU_DCR6
`ifdef OR1200_DU_DCR6
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dcr6 <= 8'h00;
                dcr6 <= 8'h00;
        else if (dcr6_sel && spr_write)
        else if (dcr6_sel && spr_write)
                dcr6 <= #1 spr_dat_i[7:0];
                dcr6 <=  spr_dat_i[7:0];
`else
`else
assign dcr6 = 8'h00;
assign dcr6 = 8'h00;
`endif
`endif
 
 
//
//
Line 860... Line 860...
`ifdef OR1200_DU_DCR7
`ifdef OR1200_DU_DCR7
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dcr7 <= 8'h00;
                dcr7 <= 8'h00;
        else if (dcr7_sel && spr_write)
        else if (dcr7_sel && spr_write)
                dcr7 <= #1 spr_dat_i[7:0];
                dcr7 <=  spr_dat_i[7:0];
`else
`else
assign dcr7 = 8'h00;
assign dcr7 = 8'h00;
`endif
`endif
 
 
//
//
Line 873... Line 873...
`ifdef OR1200_DU_DWCR0
`ifdef OR1200_DU_DWCR0
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dwcr0 <= 32'h0000_0000;
                dwcr0 <= 32'h0000_0000;
        else if (dwcr0_sel && spr_write)
        else if (dwcr0_sel && spr_write)
                dwcr0 <= #1 spr_dat_i[31:0];
                dwcr0 <=  spr_dat_i[31:0];
        else if (incr_wpcntr0)
        else if (incr_wpcntr0)
                dwcr0[`OR1200_DU_DWCR_COUNT] <= #1 dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
                dwcr0[`OR1200_DU_DWCR_COUNT] <=  dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
`else
`else
assign dwcr0 = 32'h0000_0000;
assign dwcr0 = 32'h0000_0000;
`endif
`endif
 
 
//
//
Line 888... Line 888...
`ifdef OR1200_DU_DWCR1
`ifdef OR1200_DU_DWCR1
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dwcr1 <= 32'h0000_0000;
                dwcr1 <= 32'h0000_0000;
        else if (dwcr1_sel && spr_write)
        else if (dwcr1_sel && spr_write)
                dwcr1 <= #1 spr_dat_i[31:0];
                dwcr1 <=  spr_dat_i[31:0];
        else if (incr_wpcntr1)
        else if (incr_wpcntr1)
                dwcr1[`OR1200_DU_DWCR_COUNT] <= #1 dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
                dwcr1[`OR1200_DU_DWCR_COUNT] <=  dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
`else
`else
assign dwcr1 = 32'h0000_0000;
assign dwcr1 = 32'h0000_0000;
`endif
`endif
 
 
//
//
Line 1620... Line 1620...
`endif
`endif
 
 
// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception 
// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception 
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                du_hwbkpt_hold <= #1 1'b0;
                du_hwbkpt_hold <=  1'b0;
        else if (du_hwbkpt & ex_freeze)
        else if (du_hwbkpt & ex_freeze)
                du_hwbkpt_hold <= #1 1'b1;
                du_hwbkpt_hold <=  1'b1;
        else if (!ex_freeze)
        else if (!ex_freeze)
                du_hwbkpt_hold <= #1 1'b0;
                du_hwbkpt_hold <=  1'b0;
 
 
`ifdef OR1200_DU_TB_IMPLEMENTED
`ifdef OR1200_DU_TB_IMPLEMENTED
//
//
// Simple trace buffer
// Simple trace buffer
// (right now hardcoded for Xilinx Virtex FPGAs)
// (right now hardcoded for Xilinx Virtex FPGAs)
Line 1645... Line 1645...
//
//
// Trace buffer write address pointer
// Trace buffer write address pointer
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                tb_wadr <= #1 8'h00;
                tb_wadr <=  8'h00;
        else if (tb_enw)
        else if (tb_enw)
                tb_wadr <= #1 tb_wadr + 8'd1;
                tb_wadr <=  tb_wadr + 8'd1;
 
 
//
//
// Free running counter (time stamp)
// Free running counter (time stamp)
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                tb_timstmp <= #1 32'h00000000;
                tb_timstmp <=  32'h00000000;
        else if (!dbg_bp_r)
        else if (!dbg_bp_r)
                tb_timstmp <= #1 tb_timstmp + 32'd1;
                tb_timstmp <=  tb_timstmp + 32'd1;
 
 
//
//
// Trace buffer RAMs
// Trace buffer RAMs
//
//
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.