| Line 1... |
Line 1... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Exception logic ////
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//// OR1200's Exception logic ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Handles all OR1K exceptions inside CPU block. ////
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//// Handles all OR1K exceptions inside CPU block. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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| Line 39... |
Line 39... |
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// $Log: or1200_except.v,v $
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// $Log: or1200_except.v,v $
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//
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//
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Major update:
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// Structure reordered and bugs fixed.
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// Structure reordered and bugs fixed.
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//
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// Revision 1.17 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.16 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.15.4.1 2004/02/11 01:40:11 lampret
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// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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//
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// Revision 1.15 2003/04/20 22:23:57 lampret
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// No functional change. Only added customization for exception vectors.
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//
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// Revision 1.14 2002/09/03 22:28:21 lampret
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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//
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// Revision 1.13 2002/08/28 01:44:25 lampret
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// Removed some commented RTL. Fixed SR/ESR flag bug.
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//
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// Revision 1.12 2002/08/22 02:16:45 lampret
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// Fixed IMMU bug.
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//
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// Revision 1.11 2002/08/18 19:54:28 lampret
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// Added store buffer.
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//
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// Revision 1.10 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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// Revision 1.9 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.8 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.7 2002/01/23 07:52:36 lampret
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// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
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//
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// Revision 1.6 2002/01/18 14:21:43 lampret
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// Fixed 'the NPC single-step fix'.
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//
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// Revision 1.5 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.4 2002/01/14 21:11:50 lampret
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// Changed alignment exception EPCR. Not tested yet.
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//
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// Revision 1.3 2002/01/14 19:09:57 lampret
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// Fixed order of syscall and range exceptions.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.15 2001/11/27 23:13:11 lampret
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// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
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//
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// Revision 1.14 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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//
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// Revision 1.13 2001/11/20 18:46:15 simons
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// Break point bug fixed
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//
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// Revision 1.12 2001/11/18 09:58:28 lampret
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// Fixed some l.trap typos.
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//
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// Revision 1.11 2001/11/18 08:36:28 lampret
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// For GDB changed single stepping and disabled trap exception.
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//
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// Revision 1.10 2001/11/13 10:02:21 lampret
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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//
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// Revision 1.9 2001/11/10 03:43:57 lampret
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// Fixed exceptions.
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//
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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| Line 155... |
Line 62... |
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//
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//
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// Exception recognition and sequencing
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// Exception recognition and sequencing
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//
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//
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module or1200_except(
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module or1200_except
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(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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// Internal i/f
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// Internal i/f
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sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
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sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss,
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sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
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sig_dmmufault, sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault,
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ex_branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze, if_stall,
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sig_tick, ex_branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze,
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if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe, extend_flush, except_flushpipe, except_type, except_start,
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if_stall, if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe,
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except_started, except_stop, except_trig, ex_void, abort_mvspr, branch_op,
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extend_flush, except_flushpipe, except_type, except_start, except_started,
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spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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except_stop, except_trig, ex_void, abort_mvspr, branch_op, spr_dat_ppc,
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du_dmr1, du_hwbkpt, du_hwbkpt_ls_r,
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spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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esr, sr_we, to_sr, sr, lsu_addr, abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i
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du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, esr, sr_we, to_sr, sr, lsu_addr,
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abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, sig_fp, fpcsr_fpee
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);
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);
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//
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//
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// I/O
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// I/O
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| Line 190... |
Line 98... |
input sig_syscall;
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input sig_syscall;
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input sig_trap;
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input sig_trap;
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input sig_itlbmiss;
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input sig_itlbmiss;
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input sig_immufault;
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input sig_immufault;
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input sig_tick;
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input sig_tick;
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input sig_fp;
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input fpcsr_fpee;
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input ex_branch_taken;
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input ex_branch_taken;
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input genpc_freeze;
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input genpc_freeze;
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input id_freeze;
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input id_freeze;
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input ex_freeze;
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input ex_freeze;
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input wb_freeze;
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input wb_freeze;
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| Line 223... |
Line 133... |
output except_flushpipe;
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output except_flushpipe;
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output extend_flush;
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output extend_flush;
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output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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output except_start;
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output except_start;
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output except_started;
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output except_started;
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output [12:0] except_stop;
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output [13:0] except_stop;
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output [12:0] except_trig;
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output [13:0] except_trig;
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input ex_void;
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input ex_void;
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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output [31:0] spr_dat_ppc;
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output [31:0] spr_dat_ppc;
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output [31:0] spr_dat_npc;
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output [31:0] spr_dat_npc;
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output abort_ex;
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output abort_ex;
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| Line 262... |
Line 172... |
wire except_started;
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wire except_started;
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reg [2:0] delayed_iee;
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reg [2:0] delayed_iee;
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reg [2:0] delayed_tee;
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reg [2:0] delayed_tee;
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wire int_pending;
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wire int_pending;
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wire tick_pending;
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wire tick_pending;
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wire fp_pending;
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reg trace_trap ;
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reg trace_trap ;
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reg ex_freeze_prev;
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reg ex_freeze_prev;
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reg sr_ted_prev;
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reg sr_ted_prev;
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reg dsr_te_prev;
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reg dsr_te_prev;
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reg dmr1_st_prev ;
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reg dmr1_st_prev ;
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| Line 277... |
Line 189... |
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//
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//
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// Simple combinatorial logic
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// Simple combinatorial logic
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//
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//
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assign except_started = extend_flush & except_start;
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assign except_started = extend_flush & except_start;
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assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
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assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
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assign int_pending = sig_int & (sr[`OR1200_SR_IEE] | (sr_we & to_sr[`OR1200_SR_IEE])) & id_pc_val & delayed_iee[2] & ~ex_freeze & ~ex_branch_taken & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_IEE]);
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assign tick_pending = sig_tick & (sr[`OR1200_SR_TEE] | (sr_we & to_sr[`OR1200_SR_TEE])) & id_pc_val & delayed_tee[2] & ~ex_freeze & ~ex_branch_taken & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]);
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assign int_pending = sig_int & (sr[`OR1200_SR_IEE] |
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assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val & !sr_ted & !dsr_te); // Abort write into RF by load & other instructions
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(sr_we & to_sr[`OR1200_SR_IEE]))
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assign abort_mvspr = sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val & !sr_ted & !dsr_te) ; // abort spr read/writes
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& id_pc_val & delayed_iee[2] & ~ex_freeze & ~ex_branch_taken
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& ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_IEE]);
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assign tick_pending = sig_tick & (sr[`OR1200_SR_TEE] |
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(sr_we & to_sr[`OR1200_SR_TEE])) & id_pc_val
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& delayed_tee[2] & ~ex_freeze & ~ex_branch_taken
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& ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]);
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assign fp_pending = sig_fp & fpcsr_fpee & ~ex_freeze & ~ex_branch_taken
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& ~ex_dslot;
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// Abort write into RF by load & other instructions
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assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align |
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sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val
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& !sr_ted & !dsr_te);
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// abort spr read/writes
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assign abort_mvspr = sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val
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& !sr_ted & !dsr_te) ;
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assign spr_dat_ppc = wb_pc;
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assign spr_dat_ppc = wb_pc;
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assign spr_dat_npc = ex_void ? id_pc : ex_pc;
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assign spr_dat_npc = ex_void ? id_pc : ex_pc;
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|
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//
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//
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// Order defines exception detection priority
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// Order defines exception detection priority
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//
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//
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| Line 300... |
Line 232... |
sig_trap & ~du_dsr[`OR1200_DU_DSR_TE],
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sig_trap & ~du_dsr[`OR1200_DU_DSR_TE],
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sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
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sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
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sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
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sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
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fp_pending & ~du_dsr[`OR1200_DU_DSR_FPE],
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int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
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int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
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tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE]
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tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE]
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};
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};
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wire trace_cond = !ex_freeze && !ex_void && (1'b0
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wire trace_cond = !ex_freeze && !ex_void && (1'b0
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`ifdef OR1200_DU_DMR1_ST
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`ifdef OR1200_DU_DMR1_ST
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|| dmr1_st
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|| dmr1_st
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`endif
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`endif
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`ifdef OR1200_DU_DMR1_BT
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`ifdef OR1200_DU_DMR1_BT
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| Line 325... |
Line 259... |
sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
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sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
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sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_range & du_dsr[`OR1200_DU_DSR_RE],
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sig_range & du_dsr[`OR1200_DU_DSR_RE],
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sig_trap & du_dsr[`OR1200_DU_DSR_TE],
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sig_trap & du_dsr[`OR1200_DU_DSR_TE],
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fp_pending & du_dsr[`OR1200_DU_DSR_FPE],
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sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
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sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
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};
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};
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|
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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if (rst) begin
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| Line 495... |
Line 430... |
state <= #1 `OR1200_EXCEPTFSM_FLU1;
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state <= #1 `OR1200_EXCEPTFSM_FLU1;
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extend_flush <= #1 1'b1;
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extend_flush <= #1 1'b1;
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esr <= #1 sr_we ? to_sr : sr;
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esr <= #1 sr_we ? to_sr : sr;
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casex (except_trig)
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casex (except_trig)
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`ifdef OR1200_EXCEPT_ITLBMISS
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`ifdef OR1200_EXCEPT_ITLBMISS
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13'b1_xxxx_xxxx_xxxx: begin
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14'b1x_xxxx_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
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except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
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eear <= #1 ex_dslot ? ex_pc : ex_pc;
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eear <= #1 ex_dslot ?
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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ex_pc : ex_pc;
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epcr <= #1 ex_dslot ?
|
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wb_pc : ex_pc;
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end
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end
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`endif
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`endif
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`ifdef OR1200_EXCEPT_IPF
|
`ifdef OR1200_EXCEPT_IPF
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13'b0_1xxx_xxxx_xxxx: begin
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14'b01_xxxx_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_IPF;
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except_type <= #1 `OR1200_EXCEPT_IPF;
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eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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eear <= #1 ex_dslot ?
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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ex_pc : delayed1_ex_dslot ?
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id_pc : delayed2_ex_dslot ?
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id_pc : id_pc;
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epcr <= #1 ex_dslot ?
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wb_pc : delayed1_ex_dslot ?
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id_pc : delayed2_ex_dslot ?
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id_pc : id_pc;
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end
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end
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`endif
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`endif
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`ifdef OR1200_EXCEPT_BUSERR
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`ifdef OR1200_EXCEPT_BUSERR
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13'b0_01xx_xxxx_xxxx: begin
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14'b00_1xxx_xxxx_xxxx: begin // Insn. Bus Error
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except_type <= #1 `OR1200_EXCEPT_BUSERR;
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except_type <= #1 `OR1200_EXCEPT_BUSERR;
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eear <= #1 ex_dslot ? wb_pc : ex_pc;
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eear <= #1 ex_dslot ?
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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wb_pc : ex_pc;
|
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epcr <= #1 ex_dslot ?
|
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wb_pc : ex_pc;
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end
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end
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`endif
|
`endif
|
`ifdef OR1200_EXCEPT_ILLEGAL
|
`ifdef OR1200_EXCEPT_ILLEGAL
|
13'b0_001x_xxxx_xxxx: begin
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14'b00_01xx_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
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except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
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eear <= #1 ex_pc;
|
eear <= #1 ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ?
|
|
wb_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_ALIGN
|
`ifdef OR1200_EXCEPT_ALIGN
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13'b0_0001_xxxx_xxxx: begin
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14'b00_001x_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_ALIGN;
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except_type <= #1 `OR1200_EXCEPT_ALIGN;
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eear <= #1 lsu_addr;
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eear <= #1 lsu_addr;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ?
|
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wb_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_DTLBMISS
|
`ifdef OR1200_EXCEPT_DTLBMISS
|
13'b0_0000_1xxx_xxxx: begin
|
14'b00_0001_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
|
except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
|
eear <= #1 lsu_addr;
|
eear <= #1 lsu_addr;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
|
epcr <= #1 ex_dslot ?
|
|
wb_pc : delayed1_ex_dslot ?
|
|
dl_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_TRAP 13'b0_0000_01xx_xxxx: begin
|
`ifdef OR1200_EXCEPT_TRAP
|
|
14'b00_0000_1xxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_TRAP;
|
except_type <= #1 `OR1200_EXCEPT_TRAP;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : ex_pc;
|
epcr <= #1 ex_dslot ?
|
|
wb_pc : delayed1_ex_dslot ?
|
|
id_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_SYSCALL
|
`ifdef OR1200_EXCEPT_SYSCALL
|
13'b0_0000_001x_xxxx: begin
|
14'b00_0000_01xx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_SYSCALL;
|
except_type <= #1 `OR1200_EXCEPT_SYSCALL;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ?
|
|
wb_pc : delayed1_ex_dslot ?
|
|
id_pc : delayed2_ex_dslot ?
|
|
id_pc : id_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_DPF
|
`ifdef OR1200_EXCEPT_DPF
|
13'b0_0000_0001_xxxx: begin
|
14'b00_0000_001x_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_DPF;
|
except_type <= #1 `OR1200_EXCEPT_DPF;
|
eear <= #1 lsu_addr;
|
eear <= #1 lsu_addr;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
|
epcr <= #1 ex_dslot ?
|
|
wb_pc : delayed1_ex_dslot ?
|
|
dl_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_BUSERR
|
`ifdef OR1200_EXCEPT_BUSERR
|
13'b0_0000_0000_1xxx: begin // Data Bus Error
|
14'b00_0000_0001_xxxx: begin // Data Bus Error
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
eear <= #1 lsu_addr;
|
eear <= #1 lsu_addr;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
|
epcr <= #1 ex_dslot ?
|
|
wb_pc : delayed1_ex_dslot ?
|
|
dl_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_RANGE
|
`ifdef OR1200_EXCEPT_RANGE
|
13'b0_0000_0000_01xx: begin
|
14'b00_0000_0000_1xxx: begin
|
except_type <= #1 `OR1200_EXCEPT_RANGE;
|
except_type <= #1 `OR1200_EXCEPT_RANGE;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ?
|
|
wb_pc : delayed1_ex_dslot ?
|
|
id_pc : delayed2_ex_dslot ?
|
|
id_pc : id_pc;
|
|
end
|
|
`endif
|
|
`ifdef OR1200_EXCEPT_FLOAT
|
|
14'b00_0000_0000_01xx: begin
|
|
except_type <= #1 `OR1200_EXCEPT_FLOAT;
|
|
epcr <= #1 id_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_INT
|
`ifdef OR1200_EXCEPT_INT
|
13'b0_0000_0000_001x: begin
|
14'b00_0000_0000_001x: begin
|
except_type <= #1 `OR1200_EXCEPT_INT;
|
except_type <= #1 `OR1200_EXCEPT_INT;
|
epcr <= #1 id_pc;
|
epcr <= #1 id_pc;
|
//epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_TICK
|
`ifdef OR1200_EXCEPT_TICK
|
13'b0_0000_0000_0001: begin
|
14'b00_0000_0000_0001: begin
|
except_type <= #1 `OR1200_EXCEPT_TICK;
|
except_type <= #1 `OR1200_EXCEPT_TICK;
|
epcr <= #1 id_pc;
|
epcr <= #1 id_pc;
|
//epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
|
end
|
end
|
`endif
|
`endif
|
|
|
default:
|
default:
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
endcase
|
endcase
|
end
|
end
|
else if (pc_we) begin
|
else if (pc_we) begin
|
