| Line 149... |
Line 149... |
input dcpu_err_i;
|
input dcpu_err_i;
|
|
|
//
|
//
|
// Internal regs and wires
|
// Internal regs and wires
|
//
|
//
|
reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
|
reg [`OR1200_EXCEPT_WIDTH-1:0] except_type /* verilator public */;
|
reg [31:0] id_pc;
|
reg [31:0] id_pc /* verilator public */;
|
reg id_pc_val;
|
reg id_pc_val;
|
reg [31:0] ex_pc;
|
reg [31:0] ex_pc /* verilator public */;
|
reg ex_pc_val;
|
reg ex_pc_val;
|
reg [31:0] wb_pc;
|
reg [31:0] wb_pc /* verilator public */;
|
reg [31:0] dl_pc;
|
reg [31:0] dl_pc;
|
reg [31:0] epcr;
|
reg [31:0] epcr;
|
reg [31:0] eear;
|
reg [31:0] eear;
|
reg [`OR1200_SR_WIDTH-1:0] esr;
|
reg [`OR1200_SR_WIDTH-1:0] esr;
|
reg [2:0] id_exceptflags;
|
reg [2:0] id_exceptflags;
|
reg [2:0] ex_exceptflags;
|
reg [2:0] ex_exceptflags;
|
reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
|
reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
|
reg extend_flush;
|
reg extend_flush;
|
reg extend_flush_last;
|
reg extend_flush_last;
|
reg ex_dslot;
|
reg ex_dslot /* verilator public */;
|
reg delayed1_ex_dslot;
|
reg delayed1_ex_dslot;
|
reg delayed2_ex_dslot;
|
reg delayed2_ex_dslot;
|
wire except_started;
|
wire except_started;
|
|
wire except_flushpipe /* verilator public */;
|
reg [2:0] delayed_iee;
|
reg [2:0] delayed_iee;
|
reg [2:0] delayed_tee;
|
reg [2:0] delayed_tee;
|
wire int_pending;
|
wire int_pending;
|
wire tick_pending;
|
wire tick_pending;
|
wire fp_pending;
|
wire fp_pending;
|
| Line 291... |
Line 292... |
dmr1_bt_prev <= du_dmr1[`OR1200_DU_DMR1_BT] ;
|
dmr1_bt_prev <= du_dmr1[`OR1200_DU_DMR1_BT] ;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
`ifdef verilator
|
|
// Function to access wb_pc (for Verilator). Have to hide this from
|
|
// simulator, since functions with no inputs are not allowed in IEEE
|
|
// 1364-2001.
|
|
function [31:0] get_wb_pc;
|
|
// verilator public
|
|
get_wb_pc = wb_pc;
|
|
endfunction // get_wb_pc
|
|
|
|
// Function to access id_pc (for Verilator). Have to hide this from
|
|
// simulator, since functions with no inputs are not allowed in IEEE
|
|
// 1364-2001.
|
|
function [31:0] get_id_pc;
|
|
// verilator public
|
|
get_id_pc = id_pc;
|
|
endfunction // get_id_pc
|
|
|
|
// Function to access ex_pc (for Verilator). Have to hide this from
|
|
// simulator, since functions with no inputs are not allowed in IEEE
|
|
// 1364-2001.
|
|
function [31:0] get_ex_pc;
|
|
// verilator public
|
|
get_ex_pc = ex_pc;
|
|
endfunction // get_ex_pc
|
|
// Function to access except_type[3:0] (for Verilator). Have to hide this from
|
|
// simulator, since functions with no inputs are not allowed in IEEE
|
|
// 1364-2001.
|
|
function [3:0] get_except_type;
|
|
// verilator public
|
|
get_except_type = except_type;
|
|
endfunction // get_except_type
|
|
|
|
`endif
|
|
|
|
|
//
|
//
|
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
