| Line 264... |
Line 264... |
sig_trap & du_dsr[`OR1200_DU_DSR_TE],
|
sig_trap & du_dsr[`OR1200_DU_DSR_TE],
|
fp_pending & du_dsr[`OR1200_DU_DSR_FPE],
|
fp_pending & du_dsr[`OR1200_DU_DSR_FPE],
|
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
};
|
};
|
|
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
trace_trap <= 1'b0 ;
|
trace_trap <= 1'b0 ;
|
end
|
end
|
else if (!(trace_trap && !ex_pc_val)) begin
|
else if (!(trace_trap && !ex_pc_val)) begin
|
trace_trap <= trace_cond & !dsr_te & !sr_ted ;
|
trace_trap <= trace_cond & !dsr_te & !sr_ted ;
|
end
|
end
|
end
|
end
|
|
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
ex_freeze_prev <= 1'b0 ;
|
ex_freeze_prev <= 1'b0 ;
|
sr_ted_prev <= 1'b0 ;
|
sr_ted_prev <= 1'b0 ;
|
dsr_te_prev <= 1'b0 ;
|
dsr_te_prev <= 1'b0 ;
|
dmr1_st_prev <= 1'b0 ;
|
dmr1_st_prev <= 1'b0 ;
|
dmr1_bt_prev <= 1'b0 ;
|
dmr1_bt_prev <= 1'b0 ;
|
| Line 330... |
Line 330... |
|
|
|
|
//
|
//
|
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
id_pc <= 32'd0;
|
id_pc <= 32'd0;
|
id_pc_val <= 1'b0 ;
|
id_pc_val <= 1'b0 ;
|
id_exceptflags <= 3'b000;
|
id_exceptflags <= 3'b000;
|
end
|
end
|
else if (id_flushpipe) begin
|
else if (id_flushpipe) begin
|
| Line 355... |
Line 355... |
// SR[IEE] should not enable interrupts right away
|
// SR[IEE] should not enable interrupts right away
|
// when it is restored with l.rfe. Instead delayed_iee
|
// when it is restored with l.rfe. Instead delayed_iee
|
// together with SR[IEE] enables interrupts once
|
// together with SR[IEE] enables interrupts once
|
// pipeline is again ready.
|
// pipeline is again ready.
|
//
|
//
|
always @(posedge rst or posedge clk)
|
always @(`OR1200_RST_EVENT rst or posedge clk)
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
delayed_iee <= 3'b000;
|
delayed_iee <= 3'b000;
|
else if (!sr[`OR1200_SR_IEE])
|
else if (!sr[`OR1200_SR_IEE])
|
delayed_iee <= 3'b000;
|
delayed_iee <= 3'b000;
|
else
|
else
|
delayed_iee <= {delayed_iee[1:0], 1'b1};
|
delayed_iee <= {delayed_iee[1:0], 1'b1};
|
| Line 371... |
Line 371... |
// SR[TEE] should not enable tick exceptions right away
|
// SR[TEE] should not enable tick exceptions right away
|
// when it is restored with l.rfe. Instead delayed_tee
|
// when it is restored with l.rfe. Instead delayed_tee
|
// together with SR[TEE] enables tick exceptions once
|
// together with SR[TEE] enables tick exceptions once
|
// pipeline is again ready.
|
// pipeline is again ready.
|
//
|
//
|
always @(posedge rst or posedge clk)
|
always @(`OR1200_RST_EVENT rst or posedge clk)
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
delayed_tee <= 3'b000;
|
delayed_tee <= 3'b000;
|
else if (!sr[`OR1200_SR_TEE])
|
else if (!sr[`OR1200_SR_TEE])
|
delayed_tee <= 3'b000;
|
delayed_tee <= 3'b000;
|
else
|
else
|
delayed_tee <= {delayed_tee[1:0], 1'b1};
|
delayed_tee <= {delayed_tee[1:0], 1'b1};
|
|
|
//
|
//
|
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
ex_dslot <= 1'b0;
|
ex_dslot <= 1'b0;
|
ex_pc <= 32'd0;
|
ex_pc <= 32'd0;
|
ex_pc_val <= 1'b0 ;
|
ex_pc_val <= 1'b0 ;
|
ex_exceptflags <= 3'b000;
|
ex_exceptflags <= 3'b000;
|
delayed1_ex_dslot <= 1'b0;
|
delayed1_ex_dslot <= 1'b0;
|
| Line 419... |
Line 419... |
end
|
end
|
|
|
//
|
//
|
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
wb_pc <= 32'd0;
|
wb_pc <= 32'd0;
|
dl_pc <= 32'd0;
|
dl_pc <= 32'd0;
|
end
|
end
|
else if (!wb_freeze) begin
|
else if (!wb_freeze) begin
|
wb_pc <= ex_pc;
|
wb_pc <= ex_pc;
|
| Line 443... |
Line 443... |
// Exception FSM that sequences execution of exception handler
|
// Exception FSM that sequences execution of exception handler
|
//
|
//
|
// except_type signals which exception handler we start fetching in:
|
// except_type signals which exception handler we start fetching in:
|
// 1. Asserted in next clock cycle after exception is recognized
|
// 1. Asserted in next clock cycle after exception is recognized
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
state <= `OR1200_EXCEPTFSM_IDLE;
|
state <= `OR1200_EXCEPTFSM_IDLE;
|
except_type <= `OR1200_EXCEPT_NONE;
|
except_type <= `OR1200_EXCEPT_NONE;
|
extend_flush <= 1'b0;
|
extend_flush <= 1'b0;
|
epcr <= 32'b0;
|
epcr <= 32'b0;
|
eear <= 32'b0;
|
eear <= 32'b0;
|
