| Line 76... |
Line 76... |
if_stall, if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe,
|
if_stall, if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe,
|
extend_flush, except_flushpipe, except_type, except_start, except_started,
|
extend_flush, except_flushpipe, except_type, except_start, except_started,
|
except_stop, except_trig, ex_void, abort_mvspr, branch_op, spr_dat_ppc,
|
except_stop, except_trig, ex_void, abort_mvspr, branch_op, spr_dat_ppc,
|
spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
|
spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
|
du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, esr, sr_we, to_sr, sr, lsu_addr,
|
du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, esr, sr_we, to_sr, sr, lsu_addr,
|
abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, sig_fp, fpcsr_fpee
|
abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, sig_fp, fpcsr_fpee,
|
|
dsx
|
|
|
);
|
);
|
|
|
//
|
//
|
// I/O
|
// I/O
|
| Line 145... |
Line 146... |
output abort_mvspr;
|
output abort_mvspr;
|
input icpu_ack_i;
|
input icpu_ack_i;
|
input icpu_err_i;
|
input icpu_err_i;
|
input dcpu_ack_i;
|
input dcpu_ack_i;
|
input dcpu_err_i;
|
input dcpu_err_i;
|
|
output dsx;
|
|
|
//
|
//
|
// Internal regs and wires
|
// Internal regs and wires
|
//
|
//
|
reg [`OR1200_EXCEPT_WIDTH-1:0] except_type /* verilator public */;
|
reg [`OR1200_EXCEPT_WIDTH-1:0] except_type /* verilator public */;
|
| Line 175... |
Line 177... |
reg [2:0] delayed_tee;
|
reg [2:0] delayed_tee;
|
wire int_pending;
|
wire int_pending;
|
wire tick_pending;
|
wire tick_pending;
|
wire fp_pending;
|
wire fp_pending;
|
wire range_pending;
|
wire range_pending;
|
|
reg dsx;
|
|
|
reg trace_trap ;
|
reg trace_trap ;
|
reg ex_freeze_prev;
|
reg ex_freeze_prev;
|
reg sr_ted_prev;
|
reg sr_ted_prev;
|
reg dsr_te_prev;
|
reg dsr_te_prev;
|
| Line 460... |
Line 463... |
extend_flush <= 1'b0;
|
extend_flush <= 1'b0;
|
epcr <= 32'b0;
|
epcr <= 32'b0;
|
eear <= 32'b0;
|
eear <= 32'b0;
|
esr <= {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
|
esr <= {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
|
extend_flush_last <= 1'b0;
|
extend_flush_last <= 1'b0;
|
|
dsx <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
`ifdef OR1200_CASE_DEFAULT
|
`ifdef OR1200_CASE_DEFAULT
|
case (state) // synopsys parallel_case
|
case (state) // synopsys parallel_case
|
`else
|
`else
|
| Line 480... |
Line 484... |
except_type <= `OR1200_EXCEPT_ITLBMISS;
|
except_type <= `OR1200_EXCEPT_ITLBMISS;
|
eear <= ex_dslot ?
|
eear <= ex_dslot ?
|
ex_pc : ex_pc;
|
ex_pc : ex_pc;
|
epcr <= ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : ex_pc;
|
wb_pc : ex_pc;
|
|
dsx <= ex_dslot;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_IPF
|
`ifdef OR1200_EXCEPT_IPF
|
14'b01_????_????_????: begin
|
14'b01_????_????_????: begin
|
except_type <= `OR1200_EXCEPT_IPF;
|
except_type <= `OR1200_EXCEPT_IPF;
|
| Line 493... |
Line 498... |
id_pc : id_pc;
|
id_pc : id_pc;
|
epcr <= ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
id_pc : delayed2_ex_dslot ?
|
id_pc : delayed2_ex_dslot ?
|
id_pc : id_pc;
|
id_pc : id_pc;
|
|
dsx <= ex_dslot;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_BUSERR
|
`ifdef OR1200_EXCEPT_BUSERR
|
14'b00_1???_????_????: begin // Insn. Bus Error
|
14'b00_1???_????_????: begin // Insn. Bus Error
|
except_type <= `OR1200_EXCEPT_BUSERR;
|
except_type <= `OR1200_EXCEPT_BUSERR;
|
eear <= ex_dslot ?
|
eear <= ex_dslot ?
|
wb_pc : ex_pc;
|
wb_pc : ex_pc;
|
epcr <= ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : ex_pc;
|
wb_pc : ex_pc;
|
|
dsx <= ex_dslot;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_ILLEGAL
|
`ifdef OR1200_EXCEPT_ILLEGAL
|
14'b00_01??_????_????: begin
|
14'b00_01??_????_????: begin
|
except_type <= `OR1200_EXCEPT_ILLEGAL;
|
except_type <= `OR1200_EXCEPT_ILLEGAL;
|
eear <= ex_pc;
|
eear <= ex_pc;
|
epcr <= ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : ex_pc;
|
wb_pc : ex_pc;
|
|
dsx <= ex_dslot;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_ALIGN
|
`ifdef OR1200_EXCEPT_ALIGN
|
14'b00_001?_????_????: begin
|
14'b00_001?_????_????: begin
|
except_type <= `OR1200_EXCEPT_ALIGN;
|
except_type <= `OR1200_EXCEPT_ALIGN;
|
eear <= lsu_addr;
|
eear <= lsu_addr;
|
epcr <= ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : ex_pc;
|
wb_pc : ex_pc;
|
|
dsx <= ex_dslot;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_DTLBMISS
|
`ifdef OR1200_EXCEPT_DTLBMISS
|
14'b00_0001_????_????: begin
|
14'b00_0001_????_????: begin
|
except_type <= `OR1200_EXCEPT_DTLBMISS;
|
except_type <= `OR1200_EXCEPT_DTLBMISS;
|
eear <= lsu_addr;
|
eear <= lsu_addr;
|
epcr <= ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
dl_pc : ex_pc;
|
dl_pc : ex_pc;
|
|
dsx <= ex_dslot;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_TRAP
|
`ifdef OR1200_EXCEPT_TRAP
|
14'b00_0000_1???_????: begin
|
14'b00_0000_1???_????: begin
|
except_type <= `OR1200_EXCEPT_TRAP;
|
except_type <= `OR1200_EXCEPT_TRAP;
|
epcr <= ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
id_pc : ex_pc;
|
id_pc : ex_pc;
|
|
dsx <= ex_dslot;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_SYSCALL
|
`ifdef OR1200_EXCEPT_SYSCALL
|
14'b00_0000_01??_????: begin
|
14'b00_0000_01??_????: begin
|
except_type <= `OR1200_EXCEPT_SYSCALL;
|
except_type <= `OR1200_EXCEPT_SYSCALL;
|
epcr <= ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
id_pc : delayed2_ex_dslot ?
|
id_pc : delayed2_ex_dslot ?
|
id_pc : id_pc;
|
id_pc : id_pc;
|
|
dsx <= ex_dslot;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_DPF
|
`ifdef OR1200_EXCEPT_DPF
|
14'b00_0000_001?_????: begin
|
14'b00_0000_001?_????: begin
|
except_type <= `OR1200_EXCEPT_DPF;
|
except_type <= `OR1200_EXCEPT_DPF;
|
eear <= lsu_addr;
|
eear <= lsu_addr;
|
epcr <= ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
dl_pc : ex_pc;
|
dl_pc : ex_pc;
|
|
dsx <= ex_dslot;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_BUSERR
|
`ifdef OR1200_EXCEPT_BUSERR
|
14'b00_0000_0001_????: begin // Data Bus Error
|
14'b00_0000_0001_????: begin // Data Bus Error
|
except_type <= `OR1200_EXCEPT_BUSERR;
|
except_type <= `OR1200_EXCEPT_BUSERR;
|
eear <= lsu_addr;
|
eear <= lsu_addr;
|
epcr <= ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
dl_pc : ex_pc;
|
dl_pc : ex_pc;
|
|
dsx <= ex_dslot;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_RANGE
|
`ifdef OR1200_EXCEPT_RANGE
|
14'b00_0000_0000_1???: begin
|
14'b00_0000_0000_1???: begin
|
except_type <= `OR1200_EXCEPT_RANGE;
|
except_type <= `OR1200_EXCEPT_RANGE;
|
epcr <= ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
dl_pc : delayed2_ex_dslot ?
|
dl_pc : delayed2_ex_dslot ?
|
id_pc : ex_pc;
|
id_pc : ex_pc;
|
|
dsx <= ex_dslot;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_FLOAT
|
`ifdef OR1200_EXCEPT_FLOAT
|
14'b00_0000_0000_01??: begin
|
14'b00_0000_0000_01??: begin
|
except_type <= `OR1200_EXCEPT_FLOAT;
|
except_type <= `OR1200_EXCEPT_FLOAT;
|
epcr <= id_pc;
|
epcr <= id_pc;
|
|
dsx <= ex_dslot;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_INT
|
`ifdef OR1200_EXCEPT_INT
|
14'b00_0000_0000_001?: begin
|
14'b00_0000_0000_001?: begin
|
except_type <= `OR1200_EXCEPT_INT;
|
except_type <= `OR1200_EXCEPT_INT;
|
epcr <= id_pc;
|
epcr <= id_pc;
|
|
dsx <= ex_dslot;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_TICK
|
`ifdef OR1200_EXCEPT_TICK
|
14'b00_0000_0000_0001: begin
|
14'b00_0000_0000_0001: begin
|
except_type <= `OR1200_EXCEPT_TICK;
|
except_type <= `OR1200_EXCEPT_TICK;
|
epcr <= id_pc;
|
epcr <= id_pc;
|
|
dsx <= ex_dslot;
|
end
|
end
|
`endif
|
`endif
|
default:
|
default:
|
except_type <= `OR1200_EXCEPT_NONE;
|
except_type <= `OR1200_EXCEPT_NONE;
|
endcase
|
endcase
|
