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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_except.v] - Diff between revs 141 and 151

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Rev 141 Rev 151
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//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
 
// $Log: or1200_except.v,v $
// $Log: or1200_except.v,v $
 
//
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Major update: 
// Major update: 
// Structure reordered and bugs fixed. 
// Structure reordered and bugs fixed. 
//
//
// Revision 1.17  2004/06/08 18:17:36  lampret
// Revision 1.17  2004/06/08 18:17:36  lampret
Line 289... Line 289...
 
 
//
//
// Order defines exception detection priority
// Order defines exception detection priority
//
//
assign except_trig = {
assign except_trig = {
                        tick_pending            & ~du_dsr[`OR1200_DU_DSR_TTE],
 
                        int_pending             & ~du_dsr[`OR1200_DU_DSR_IE],
 
                        ex_exceptflags[1]       & ~du_dsr[`OR1200_DU_DSR_IME],
                        ex_exceptflags[1]       & ~du_dsr[`OR1200_DU_DSR_IME],
                        ex_exceptflags[0]        & ~du_dsr[`OR1200_DU_DSR_IPFE],
                        ex_exceptflags[0]        & ~du_dsr[`OR1200_DU_DSR_IPFE],
                        ex_exceptflags[2]       & ~du_dsr[`OR1200_DU_DSR_BUSEE],
                        ex_exceptflags[2]       & ~du_dsr[`OR1200_DU_DSR_BUSEE],
                        sig_illegal             & ~du_dsr[`OR1200_DU_DSR_IIE],
                        sig_illegal             & ~du_dsr[`OR1200_DU_DSR_IIE],
                        sig_align               & ~du_dsr[`OR1200_DU_DSR_AE],
                        sig_align               & ~du_dsr[`OR1200_DU_DSR_AE],
                        sig_dtlbmiss            & ~du_dsr[`OR1200_DU_DSR_DME],
                        sig_dtlbmiss            & ~du_dsr[`OR1200_DU_DSR_DME],
 
                      sig_trap          & ~du_dsr[`OR1200_DU_DSR_TE],
 
                      sig_syscall               & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
                        sig_dmmufault           & ~du_dsr[`OR1200_DU_DSR_DPFE],
                        sig_dmmufault           & ~du_dsr[`OR1200_DU_DSR_DPFE],
                        sig_dbuserr             & ~du_dsr[`OR1200_DU_DSR_BUSEE],
                        sig_dbuserr             & ~du_dsr[`OR1200_DU_DSR_BUSEE],
                        sig_range               & ~du_dsr[`OR1200_DU_DSR_RE],
                        sig_range               & ~du_dsr[`OR1200_DU_DSR_RE],
                        sig_trap                & ~du_dsr[`OR1200_DU_DSR_TE],
                      int_pending               & ~du_dsr[`OR1200_DU_DSR_IE],
                        sig_syscall             & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
                      tick_pending              & ~du_dsr[`OR1200_DU_DSR_TTE]
                };
                };
wire    trace_cond  = !ex_freeze && !ex_void && (1'b0
wire    trace_cond  = !ex_freeze && !ex_void && (1'b0
`ifdef OR1200_DU_DMR1_ST
`ifdef OR1200_DU_DMR1_ST
    ||  dmr1_st
    ||  dmr1_st
`endif
`endif
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                                if (except_flushpipe) begin
                                if (except_flushpipe) begin
                                        state <= #1 `OR1200_EXCEPTFSM_FLU1;
                                        state <= #1 `OR1200_EXCEPTFSM_FLU1;
                                        extend_flush <= #1 1'b1;
                                        extend_flush <= #1 1'b1;
                                        esr <= #1 sr_we ? to_sr : sr;
                                        esr <= #1 sr_we ? to_sr : sr;
                                        casex (except_trig)
                                        casex (except_trig)
`ifdef OR1200_EXCEPT_TICK
 
                                                13'b1_xxxx_xxxx_xxxx: begin
 
                                                        except_type <= #1 `OR1200_EXCEPT_TICK;
 
                                                        epcr <= #1 id_pc;
 
                                                        //epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
 
                                                end
 
`endif
 
`ifdef OR1200_EXCEPT_INT
 
                                                13'b0_1xxx_xxxx_xxxx: begin
 
                                                        except_type <= #1 `OR1200_EXCEPT_INT;
 
                                                        epcr <= #1 id_pc;
 
                                                        //epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
 
                                                end
 
`endif
 
`ifdef OR1200_EXCEPT_ITLBMISS
`ifdef OR1200_EXCEPT_ITLBMISS
                                                13'b0_01xx_xxxx_xxxx: begin
                                                13'b1_xxxx_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
                                                        except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
                                                        eear <= #1 ex_dslot ? ex_pc : ex_pc;
                                                        eear <= #1 ex_dslot ? ex_pc : ex_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                end
`endif
`endif
`ifdef OR1200_EXCEPT_IPF
`ifdef OR1200_EXCEPT_IPF
                                                13'b0_001x_xxxx_xxxx: begin
                                                13'b0_1xxx_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_IPF;
                                                        except_type <= #1 `OR1200_EXCEPT_IPF;
                                                        eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                end
`endif
`endif
`ifdef OR1200_EXCEPT_BUSERR
`ifdef OR1200_EXCEPT_BUSERR
                                                13'b0_0001_xxxx_xxxx: begin
                                                13'b0_01xx_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_BUSERR;
                                                        except_type <= #1 `OR1200_EXCEPT_BUSERR;
                                                        eear <= #1 ex_dslot ? wb_pc : ex_pc;
                                                        eear <= #1 ex_dslot ? wb_pc : ex_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                end
`endif
`endif
`ifdef OR1200_EXCEPT_ILLEGAL
`ifdef OR1200_EXCEPT_ILLEGAL
                                                13'b0_0000_1xxx_xxxx: begin
                                                13'b0_001x_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
                                                        except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
                                                        eear <= #1 ex_pc;
                                                        eear <= #1 ex_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                end
`endif
`endif
`ifdef OR1200_EXCEPT_ALIGN
`ifdef OR1200_EXCEPT_ALIGN
                                                13'b0_0000_01xx_xxxx: begin
                                                13'b0_0001_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_ALIGN;
                                                        except_type <= #1 `OR1200_EXCEPT_ALIGN;
                                                        eear <= #1 lsu_addr;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                end
`endif
`endif
`ifdef OR1200_EXCEPT_DTLBMISS
`ifdef OR1200_EXCEPT_DTLBMISS
                                                13'b0_0000_001x_xxxx: begin
                                                13'b0_0000_1xxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
                                                        except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
                                                        eear <= #1 lsu_addr;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
                                                end
                                                end
`endif
`endif
 
`ifdef OR1200_EXCEPT_TRAP                       13'b0_0000_01xx_xxxx: begin
 
                                                        except_type <= #1 `OR1200_EXCEPT_TRAP;
 
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : ex_pc;
 
                                                end
 
`endif
 
`ifdef OR1200_EXCEPT_SYSCALL
 
                                                13'b0_0000_001x_xxxx: begin
 
                                                        except_type <= #1 `OR1200_EXCEPT_SYSCALL;
 
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
 
                                                end
 
`endif
`ifdef OR1200_EXCEPT_DPF
`ifdef OR1200_EXCEPT_DPF
                                                13'b0_0000_0001_xxxx: begin
                                                13'b0_0000_0001_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_DPF;
                                                        except_type <= #1 `OR1200_EXCEPT_DPF;
                                                        eear <= #1 lsu_addr;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
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                                                13'b0_0000_0000_01xx: begin
                                                13'b0_0000_0000_01xx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_RANGE;
                                                        except_type <= #1 `OR1200_EXCEPT_RANGE;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                end
`endif
`endif
`ifdef OR1200_EXCEPT_TRAP                       13'b0_0000_0000_001x: begin
`ifdef OR1200_EXCEPT_INT
                                                        except_type <= #1 `OR1200_EXCEPT_TRAP;
                                                13'b0_0000_0000_001x: begin
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : ex_pc;
                                                        except_type <= #1 `OR1200_EXCEPT_INT;
 
                                                        epcr <= #1 id_pc;
 
                                                        //epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                end
`endif
`endif
`ifdef OR1200_EXCEPT_SYSCALL
`ifdef OR1200_EXCEPT_TICK
                                                13'b0_0000_0000_0001: begin
                                                13'b0_0000_0000_0001: begin
                                                        except_type <= #1 `OR1200_EXCEPT_SYSCALL;
                                                        except_type <= #1 `OR1200_EXCEPT_TICK;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        epcr <= #1 id_pc;
 
                                                        //epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                end
`endif
`endif
 
 
                                                default:
                                                default:
                                                        except_type <= #1 `OR1200_EXCEPT_NONE;
                                                        except_type <= #1 `OR1200_EXCEPT_NONE;
                                        endcase
                                        endcase
                                end
                                end
                                else if (pc_we) begin
                                else if (pc_we) begin

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