| Line 41... |
Line 41... |
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
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//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: or1200_except.v,v $
|
|
// Revision 2.0 2010/06/30 11:00:00 ORSoC
|
|
// Major update:
|
|
// Structure reordered and bugs fixed.
|
|
//
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|
// Revision 1.17 2004/06/08 18:17:36 lampret
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|
// Non-functional changes. Coding style fixes.
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|
//
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// Revision 1.16 2004/04/05 08:29:57 lampret
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// Revision 1.16 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
|
// Merged branch_qmem into main tree.
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//
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//
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// Revision 1.15.4.1 2004/02/11 01:40:11 lampret
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// Revision 1.15.4.1 2004/02/11 01:40:11 lampret
|
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
|
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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| Line 155... |
Line 162... |
clk, rst,
|
clk, rst,
|
|
|
// Internal i/f
|
// Internal i/f
|
sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
|
sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
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sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
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sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
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branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze, if_stall,
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ex_branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze, if_stall,
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if_pc, id_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
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if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe, extend_flush, except_flushpipe, except_type, except_start,
|
except_started, except_stop, ex_void,
|
except_started, except_stop, except_trig, ex_void, abort_mvspr, branch_op,
|
spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
|
|
du_dmr1, du_hwbkpt, du_hwbkpt_ls_r,
|
esr, sr_we, to_sr, sr, lsu_addr, abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i
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esr, sr_we, to_sr, sr, lsu_addr, abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i
|
|
|
|
|
);
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);
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|
|
//
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//
|
// I/O
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// I/O
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//
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//
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| Line 180... |
Line 190... |
input sig_syscall;
|
input sig_syscall;
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input sig_trap;
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input sig_trap;
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input sig_itlbmiss;
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input sig_itlbmiss;
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input sig_immufault;
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input sig_immufault;
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input sig_tick;
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input sig_tick;
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input branch_taken;
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input ex_branch_taken;
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input genpc_freeze;
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input genpc_freeze;
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input id_freeze;
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input id_freeze;
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input ex_freeze;
|
input ex_freeze;
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input wb_freeze;
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input wb_freeze;
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input if_stall;
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input if_stall;
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input [31:0] if_pc;
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input [31:0] if_pc;
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output [31:0] id_pc;
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output [31:0] id_pc;
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output [31:2] lr_sav;
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output [31:0] ex_pc;
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output [31:0] wb_pc;
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input [31:0] datain;
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input [31:0] datain;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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|
input [24:0] du_dmr1;
|
|
input du_hwbkpt;
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input du_hwbkpt_ls_r;
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input epcr_we;
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input epcr_we;
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input eear_we;
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input eear_we;
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input esr_we;
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input esr_we;
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input pc_we;
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input pc_we;
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output [31:0] epcr;
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output [31:0] epcr;
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| Line 202... |
Line 216... |
output [`OR1200_SR_WIDTH-1:0] esr;
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output [`OR1200_SR_WIDTH-1:0] esr;
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input [`OR1200_SR_WIDTH-1:0] to_sr;
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input [`OR1200_SR_WIDTH-1:0] to_sr;
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input sr_we;
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input sr_we;
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input [`OR1200_SR_WIDTH-1:0] sr;
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input [`OR1200_SR_WIDTH-1:0] sr;
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input [31:0] lsu_addr;
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input [31:0] lsu_addr;
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output flushpipe;
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input id_flushpipe;
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input ex_flushpipe;
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output except_flushpipe;
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output extend_flush;
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output extend_flush;
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output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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output except_start;
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output except_start;
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output except_started;
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output except_started;
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output [12:0] except_stop;
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output [12:0] except_stop;
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output [12:0] except_trig;
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input ex_void;
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input ex_void;
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
|
output [31:0] spr_dat_ppc;
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output [31:0] spr_dat_ppc;
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output [31:0] spr_dat_npc;
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output [31:0] spr_dat_npc;
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output abort_ex;
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output abort_ex;
|
|
output abort_mvspr;
|
input icpu_ack_i;
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input icpu_ack_i;
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input icpu_err_i;
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input icpu_err_i;
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input dcpu_ack_i;
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input dcpu_ack_i;
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input dcpu_err_i;
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input dcpu_err_i;
|
|
|
//
|
//
|
// Internal regs and wires
|
// Internal regs and wires
|
//
|
//
|
reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
|
reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
|
reg [31:0] id_pc;
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reg [31:0] id_pc;
|
|
reg id_pc_val;
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reg [31:0] ex_pc;
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reg [31:0] ex_pc;
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|
reg ex_pc_val;
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reg [31:0] wb_pc;
|
reg [31:0] wb_pc;
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|
reg [31:0] dl_pc;
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reg [31:0] epcr;
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reg [31:0] epcr;
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reg [31:0] eear;
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reg [31:0] eear;
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reg [`OR1200_SR_WIDTH-1:0] esr;
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reg [`OR1200_SR_WIDTH-1:0] esr;
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reg [2:0] id_exceptflags;
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reg [2:0] id_exceptflags;
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reg [2:0] ex_exceptflags;
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reg [2:0] ex_exceptflags;
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| Line 236... |
Line 258... |
reg extend_flush_last;
|
reg extend_flush_last;
|
reg ex_dslot;
|
reg ex_dslot;
|
reg delayed1_ex_dslot;
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reg delayed1_ex_dslot;
|
reg delayed2_ex_dslot;
|
reg delayed2_ex_dslot;
|
wire except_started;
|
wire except_started;
|
wire [12:0] except_trig;
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|
wire except_flushpipe;
|
|
reg [2:0] delayed_iee;
|
reg [2:0] delayed_iee;
|
reg [2:0] delayed_tee;
|
reg [2:0] delayed_tee;
|
wire int_pending;
|
wire int_pending;
|
wire tick_pending;
|
wire tick_pending;
|
|
reg trace_trap ;
|
|
reg ex_freeze_prev;
|
|
reg sr_ted_prev;
|
|
reg dsr_te_prev;
|
|
reg dmr1_st_prev ;
|
|
reg dmr1_bt_prev ;
|
|
wire dsr_te = ex_freeze_prev ? dsr_te_prev : du_dsr[`OR1200_DU_DSR_TE];
|
|
wire sr_ted = ex_freeze_prev ? sr_ted_prev : sr[`OR1200_SR_TED];
|
|
wire dmr1_st = ex_freeze_prev ? dmr1_st_prev: du_dmr1[`OR1200_DU_DMR1_ST] ;
|
|
wire dmr1_bt = ex_freeze_prev ? dmr1_bt_prev: du_dmr1[`OR1200_DU_DMR1_BT] ;
|
|
|
//
|
//
|
// Simple combinatorial logic
|
// Simple combinatorial logic
|
//
|
//
|
assign except_started = extend_flush & except_start;
|
assign except_started = extend_flush & except_start;
|
assign lr_sav = ex_pc[31:2];
|
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
|
|
assign int_pending = sig_int & (sr[`OR1200_SR_IEE] | (sr_we & to_sr[`OR1200_SR_IEE])) & id_pc_val & delayed_iee[2] & ~ex_freeze & ~ex_branch_taken & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_IEE]);
|
|
assign tick_pending = sig_tick & (sr[`OR1200_SR_TEE] | (sr_we & to_sr[`OR1200_SR_TEE])) & id_pc_val & delayed_tee[2] & ~ex_freeze & ~ex_branch_taken & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]);
|
|
assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val & !sr_ted & !dsr_te); // Abort write into RF by load & other instructions
|
|
assign abort_mvspr = sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val & !sr_ted & !dsr_te) ; // abort spr read/writes
|
assign spr_dat_ppc = wb_pc;
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assign spr_dat_ppc = wb_pc;
|
assign spr_dat_npc = ex_void ? id_pc : ex_pc;
|
assign spr_dat_npc = ex_void ? id_pc : ex_pc;
|
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
|
|
assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~sr_we;
|
|
assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~sr_we;
|
|
assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | sig_illegal; // Abort write into RF by load & other instructions
|
|
|
|
//
|
//
|
// Order defines exception detection priority
|
// Order defines exception detection priority
|
//
|
//
|
assign except_trig = {
|
assign except_trig = {
|
| Line 270... |
Line 300... |
sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
|
sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
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sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
|
sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
|
sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
|
sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
|
sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
|
sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
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sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
|
sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
|
sig_trap & ~du_dsr[`OR1200_DU_DSR_TE],
|
sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
};
|
};
|
|
wire trace_cond = !ex_freeze && !ex_void && (1'b0
|
|
`ifdef OR1200_DU_DMR1_ST
|
|
|| dmr1_st
|
|
`endif
|
|
`ifdef OR1200_DU_DMR1_BT
|
|
|| ((branch_op != `OR1200_BRANCHOP_NOP) && (branch_op != `OR1200_BRANCHOP_RFE) && dmr1_bt)
|
|
`endif
|
|
);
|
|
|
assign except_stop = {
|
assign except_stop = {
|
tick_pending & du_dsr[`OR1200_DU_DSR_TTE],
|
tick_pending & du_dsr[`OR1200_DU_DSR_TTE],
|
int_pending & du_dsr[`OR1200_DU_DSR_IE],
|
int_pending & du_dsr[`OR1200_DU_DSR_IE],
|
ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME],
|
ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME],
|
ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE],
|
ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE],
|
| Line 285... |
Line 324... |
sig_align & du_dsr[`OR1200_DU_DSR_AE],
|
sig_align & du_dsr[`OR1200_DU_DSR_AE],
|
sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
|
sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
|
sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
|
sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
|
sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
|
sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
|
sig_range & du_dsr[`OR1200_DU_DSR_RE],
|
sig_range & du_dsr[`OR1200_DU_DSR_RE],
|
sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
|
sig_trap & du_dsr[`OR1200_DU_DSR_TE],
|
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
};
|
};
|
|
|
|
always @(posedge clk or posedge rst) begin
|
|
if (rst) begin
|
|
trace_trap <= #1 1'b0 ;
|
|
end
|
|
else if (!(trace_trap && !ex_pc_val)) begin
|
|
trace_trap <= #1 trace_cond & !dsr_te & !sr_ted ;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk or posedge rst) begin
|
|
if (rst) begin
|
|
ex_freeze_prev <= #1 1'b0 ;
|
|
sr_ted_prev <= #1 1'b0 ;
|
|
dsr_te_prev <= #1 1'b0 ;
|
|
dmr1_st_prev <= #1 1'b0 ;
|
|
dmr1_bt_prev <= #1 1'b0 ;
|
|
end
|
|
else begin
|
|
ex_freeze_prev <= #1 ex_freeze ;
|
|
if (!ex_freeze_prev || ex_void) begin
|
|
sr_ted_prev <= #1 sr [`OR1200_SR_TED ] ;
|
|
dsr_te_prev <= #1 du_dsr [`OR1200_DU_DSR_TE ] ;
|
|
dmr1_st_prev <= #1 du_dmr1[`OR1200_DU_DMR1_ST] ;
|
|
dmr1_bt_prev <= #1 du_dmr1[`OR1200_DU_DMR1_BT] ;
|
|
end
|
|
end
|
|
end
|
|
|
//
|
//
|
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
id_pc <= #1 32'd0;
|
id_pc <= #1 32'd0;
|
|
id_pc_val <= #1 1'b0 ;
|
id_exceptflags <= #1 3'b000;
|
id_exceptflags <= #1 3'b000;
|
end
|
end
|
else if (flushpipe) begin
|
else if (id_flushpipe) begin
|
id_pc <= #1 32'h0000_0000;
|
id_pc_val <= #1 1'b0 ;
|
id_exceptflags <= #1 3'b000;
|
id_exceptflags <= #1 3'b000;
|
end
|
end
|
else if (!id_freeze) begin
|
else if (!id_freeze) begin
|
id_pc <= #1 if_pc;
|
id_pc <= #1 if_pc;
|
|
id_pc_val <= #1 1'b1 ;
|
id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault };
|
id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault };
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
| Line 346... |
Line 415... |
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
ex_dslot <= #1 1'b0;
|
ex_dslot <= #1 1'b0;
|
ex_pc <= #1 32'd0;
|
ex_pc <= #1 32'd0;
|
|
ex_pc_val <= #1 1'b0 ;
|
ex_exceptflags <= #1 3'b000;
|
ex_exceptflags <= #1 3'b000;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
end
|
end
|
else if (flushpipe) begin
|
else if (ex_flushpipe) begin
|
ex_dslot <= #1 1'b0;
|
ex_dslot <= #1 1'b0;
|
ex_pc <= #1 32'h0000_0000;
|
ex_pc_val <= #1 1'b0 ;
|
ex_exceptflags <= #1 3'b000;
|
ex_exceptflags <= #1 3'b000;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
end
|
end
|
else if (!ex_freeze & id_freeze) begin
|
else if (!ex_freeze & id_freeze) begin
|
ex_dslot <= #1 1'b0;
|
ex_dslot <= #1 1'b0;
|
ex_pc <= #1 id_pc;
|
ex_pc <= #1 id_pc;
|
|
ex_pc_val <= #1 id_pc_val ;
|
ex_exceptflags <= #1 3'b000;
|
ex_exceptflags <= #1 3'b000;
|
delayed1_ex_dslot <= #1 ex_dslot;
|
delayed1_ex_dslot <= #1 ex_dslot;
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
end
|
end
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
ex_dslot <= #1 branch_taken;
|
ex_dslot <= #1 ex_branch_taken;
|
ex_pc <= #1 id_pc;
|
ex_pc <= #1 id_pc;
|
|
ex_pc_val <= #1 id_pc_val ;
|
ex_exceptflags <= #1 id_exceptflags;
|
ex_exceptflags <= #1 id_exceptflags;
|
delayed1_ex_dslot <= #1 ex_dslot;
|
delayed1_ex_dslot <= #1 ex_dslot;
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
end
|
end
|
end
|
end
|
| Line 379... |
Line 451... |
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
wb_pc <= #1 32'd0;
|
wb_pc <= #1 32'd0;
|
|
dl_pc <= #1 32'd0;
|
end
|
end
|
else if (!wb_freeze) begin
|
else if (!wb_freeze) begin
|
wb_pc <= #1 ex_pc;
|
wb_pc <= #1 ex_pc;
|
|
dl_pc <= #1 wb_pc;
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// Flush pipeline
|
|
//
|
|
assign flushpipe = except_flushpipe | pc_we | extend_flush;
|
|
|
|
//
|
|
// We have started execution of exception handler:
|
// We have started execution of exception handler:
|
// 1. Asserted for 3 clock cycles
|
// 1. Asserted for 3 clock cycles
|
// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler
|
// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler
|
//
|
//
|
assign except_flushpipe = |except_trig & ~|state;
|
assign except_flushpipe = |except_trig & ~|state;
|
| Line 410... |
Line 479... |
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
extend_flush <= #1 1'b0;
|
extend_flush <= #1 1'b0;
|
epcr <= #1 32'b0;
|
epcr <= #1 32'b0;
|
eear <= #1 32'b0;
|
eear <= #1 32'b0;
|
esr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1};
|
esr <= #1 {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
|
extend_flush_last <= #1 1'b0;
|
extend_flush_last <= #1 1'b0;
|
end
|
end
|
else begin
|
else begin
|
`ifdef OR1200_CASE_DEFAULT
|
`ifdef OR1200_CASE_DEFAULT
|
case (state) // synopsys parallel_case
|
case (state) // synopsys parallel_case
|
| Line 428... |
Line 497... |
esr <= #1 sr_we ? to_sr : sr;
|
esr <= #1 sr_we ? to_sr : sr;
|
casex (except_trig)
|
casex (except_trig)
|
`ifdef OR1200_EXCEPT_TICK
|
`ifdef OR1200_EXCEPT_TICK
|
13'b1_xxxx_xxxx_xxxx: begin
|
13'b1_xxxx_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_TICK;
|
except_type <= #1 `OR1200_EXCEPT_TICK;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 id_pc;
|
|
//epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_INT
|
`ifdef OR1200_EXCEPT_INT
|
13'b0_1xxx_xxxx_xxxx: begin
|
13'b0_1xxx_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_INT;
|
except_type <= #1 `OR1200_EXCEPT_INT;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 id_pc;
|
|
//epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_ITLBMISS
|
`ifdef OR1200_EXCEPT_ITLBMISS
|
13'b0_01xx_xxxx_xxxx: begin
|
13'b0_01xx_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
|
except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
|
//
|
|
// itlb miss exception and active ex_dslot caused wb_pc to put into eear instead of +4 address of ex_pc (or id_pc since it was equal to ex_pc?)
|
|
// eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
|
// mmu-icdc-O2 ex_pc only OK when no ex_dslot eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
|
// mmu-icdc-O2 ex_pc only OK when no ex_dslot epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
|
eear <= #1 ex_dslot ? ex_pc : ex_pc;
|
eear <= #1 ex_dslot ? ex_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
// eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
|
// epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_IPF
|
`ifdef OR1200_EXCEPT_IPF
|
13'b0_001x_xxxx_xxxx: begin
|
13'b0_001x_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_IPF;
|
except_type <= #1 `OR1200_EXCEPT_IPF;
|
//
|
|
// ipf exception and active ex_dslot caused wb_pc to put into eear instead of +4 address of ex_pc (or id_pc since it was equal to ex_pc?)
|
|
// eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
|
eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_BUSERR
|
`ifdef OR1200_EXCEPT_BUSERR
|
| Line 486... |
Line 547... |
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_DTLBMISS
|
`ifdef OR1200_EXCEPT_DTLBMISS
|
13'b0_0000_001x_xxxx: begin
|
13'b0_0000_001x_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
|
except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
|
eear <= #1 lsu_addr;
|
eear <= #1 lsu_addr;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_DPF
|
`ifdef OR1200_EXCEPT_DPF
|
13'b0_0000_0001_xxxx: begin
|
13'b0_0000_0001_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_DPF;
|
except_type <= #1 `OR1200_EXCEPT_DPF;
|
eear <= #1 lsu_addr;
|
eear <= #1 lsu_addr;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_BUSERR
|
`ifdef OR1200_EXCEPT_BUSERR
|
13'b0_0000_0000_1xxx: begin // Data Bus Error
|
13'b0_0000_0000_1xxx: begin // Data Bus Error
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
eear <= #1 lsu_addr;
|
eear <= #1 lsu_addr;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_RANGE
|
`ifdef OR1200_EXCEPT_RANGE
|
13'b0_0000_0000_01xx: begin
|
13'b0_0000_0000_01xx: begin
|
except_type <= #1 `OR1200_EXCEPT_RANGE;
|
except_type <= #1 `OR1200_EXCEPT_RANGE;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_TRAP 13'b0_0000_0000_001x: begin
|
`ifdef OR1200_EXCEPT_TRAP 13'b0_0000_0000_001x: begin
|
except_type <= #1 `OR1200_EXCEPT_TRAP;
|
except_type <= #1 `OR1200_EXCEPT_TRAP;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_SYSCALL
|
`ifdef OR1200_EXCEPT_SYSCALL
|
13'b0_0000_0000_0001: begin
|
13'b0_0000_0000_0001: begin
|
except_type <= #1 `OR1200_EXCEPT_SYSCALL;
|
except_type <= #1 `OR1200_EXCEPT_SYSCALL;
|
| Line 534... |
Line 595... |
if (epcr_we)
|
if (epcr_we)
|
epcr <= #1 datain;
|
epcr <= #1 datain;
|
if (eear_we)
|
if (eear_we)
|
eear <= #1 datain;
|
eear <= #1 datain;
|
if (esr_we)
|
if (esr_we)
|
esr <= #1 {1'b1, datain[`OR1200_SR_WIDTH-2:0]};
|
esr <= #1 {datain[`OR1200_SR_WIDTH-1], 1'b1, datain[`OR1200_SR_WIDTH-3:0]};
|
end
|
end
|
`OR1200_EXCEPTFSM_FLU1:
|
`OR1200_EXCEPTFSM_FLU1:
|
if (icpu_ack_i | icpu_err_i | genpc_freeze)
|
if (icpu_ack_i | icpu_err_i | genpc_freeze)
|
state <= #1 `OR1200_EXCEPTFSM_FLU2;
|
state <= #1 `OR1200_EXCEPTFSM_FLU2;
|
`OR1200_EXCEPTFSM_FLU2:
|
`OR1200_EXCEPTFSM_FLU2:
|
