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Line 40... |
//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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// $Log: or1200_except.v,v $
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// $Log: or1200_except.v,v $
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//
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Major update:
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// Structure reordered and bugs fixed.
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// Structure reordered and bugs fixed.
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//
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//
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// Revision 1.17 2004/06/08 18:17:36 lampret
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// Revision 1.17 2004/06/08 18:17:36 lampret
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| Line 289... |
Line 289... |
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//
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//
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// Order defines exception detection priority
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// Order defines exception detection priority
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//
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//
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assign except_trig = {
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assign except_trig = {
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tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE],
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int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
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ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
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sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
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sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
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sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
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sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
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sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
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sig_trap & ~du_dsr[`OR1200_DU_DSR_TE],
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sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
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sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
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sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
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sig_trap & ~du_dsr[`OR1200_DU_DSR_TE],
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int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
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sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
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tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE]
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};
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};
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wire trace_cond = !ex_freeze && !ex_void && (1'b0
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wire trace_cond = !ex_freeze && !ex_void && (1'b0
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`ifdef OR1200_DU_DMR1_ST
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`ifdef OR1200_DU_DMR1_ST
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|| dmr1_st
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|| dmr1_st
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`endif
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`endif
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| Line 494... |
Line 494... |
if (except_flushpipe) begin
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if (except_flushpipe) begin
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state <= #1 `OR1200_EXCEPTFSM_FLU1;
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state <= #1 `OR1200_EXCEPTFSM_FLU1;
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extend_flush <= #1 1'b1;
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extend_flush <= #1 1'b1;
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esr <= #1 sr_we ? to_sr : sr;
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esr <= #1 sr_we ? to_sr : sr;
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casex (except_trig)
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casex (except_trig)
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`ifdef OR1200_EXCEPT_TICK
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13'b1_xxxx_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_TICK;
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epcr <= #1 id_pc;
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//epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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`endif
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`ifdef OR1200_EXCEPT_INT
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13'b0_1xxx_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_INT;
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epcr <= #1 id_pc;
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//epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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`endif
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`ifdef OR1200_EXCEPT_ITLBMISS
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`ifdef OR1200_EXCEPT_ITLBMISS
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13'b0_01xx_xxxx_xxxx: begin
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13'b1_xxxx_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
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except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
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eear <= #1 ex_dslot ? ex_pc : ex_pc;
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eear <= #1 ex_dslot ? ex_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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`endif
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`endif
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`ifdef OR1200_EXCEPT_IPF
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`ifdef OR1200_EXCEPT_IPF
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13'b0_001x_xxxx_xxxx: begin
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13'b0_1xxx_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_IPF;
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except_type <= #1 `OR1200_EXCEPT_IPF;
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eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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`endif
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`endif
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`ifdef OR1200_EXCEPT_BUSERR
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`ifdef OR1200_EXCEPT_BUSERR
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13'b0_0001_xxxx_xxxx: begin
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13'b0_01xx_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_BUSERR;
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except_type <= #1 `OR1200_EXCEPT_BUSERR;
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eear <= #1 ex_dslot ? wb_pc : ex_pc;
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eear <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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`endif
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`endif
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`ifdef OR1200_EXCEPT_ILLEGAL
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`ifdef OR1200_EXCEPT_ILLEGAL
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13'b0_0000_1xxx_xxxx: begin
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13'b0_001x_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
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except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
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eear <= #1 ex_pc;
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eear <= #1 ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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`endif
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`endif
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`ifdef OR1200_EXCEPT_ALIGN
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`ifdef OR1200_EXCEPT_ALIGN
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13'b0_0000_01xx_xxxx: begin
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13'b0_0001_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_ALIGN;
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except_type <= #1 `OR1200_EXCEPT_ALIGN;
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eear <= #1 lsu_addr;
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eear <= #1 lsu_addr;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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`endif
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`endif
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`ifdef OR1200_EXCEPT_DTLBMISS
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`ifdef OR1200_EXCEPT_DTLBMISS
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13'b0_0000_001x_xxxx: begin
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13'b0_0000_1xxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
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except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
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eear <= #1 lsu_addr;
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eear <= #1 lsu_addr;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
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end
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end
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`endif
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`endif
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`ifdef OR1200_EXCEPT_TRAP 13'b0_0000_01xx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_TRAP;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : ex_pc;
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end
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`endif
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`ifdef OR1200_EXCEPT_SYSCALL
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13'b0_0000_001x_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_SYSCALL;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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`endif
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`ifdef OR1200_EXCEPT_DPF
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`ifdef OR1200_EXCEPT_DPF
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13'b0_0000_0001_xxxx: begin
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13'b0_0000_0001_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_DPF;
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except_type <= #1 `OR1200_EXCEPT_DPF;
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eear <= #1 lsu_addr;
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eear <= #1 lsu_addr;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
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| Line 570... |
Line 567... |
13'b0_0000_0000_01xx: begin
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13'b0_0000_0000_01xx: begin
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except_type <= #1 `OR1200_EXCEPT_RANGE;
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except_type <= #1 `OR1200_EXCEPT_RANGE;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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`endif
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`endif
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`ifdef OR1200_EXCEPT_TRAP 13'b0_0000_0000_001x: begin
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`ifdef OR1200_EXCEPT_INT
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except_type <= #1 `OR1200_EXCEPT_TRAP;
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13'b0_0000_0000_001x: begin
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : ex_pc;
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except_type <= #1 `OR1200_EXCEPT_INT;
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epcr <= #1 id_pc;
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//epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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`endif
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`endif
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`ifdef OR1200_EXCEPT_SYSCALL
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`ifdef OR1200_EXCEPT_TICK
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13'b0_0000_0000_0001: begin
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13'b0_0000_0000_0001: begin
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except_type <= #1 `OR1200_EXCEPT_SYSCALL;
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except_type <= #1 `OR1200_EXCEPT_TICK;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 id_pc;
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//epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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`endif
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`endif
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default:
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default:
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except_type <= #1 `OR1200_EXCEPT_NONE;
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except_type <= #1 `OR1200_EXCEPT_NONE;
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endcase
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endcase
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end
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end
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else if (pc_we) begin
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else if (pc_we) begin
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