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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_except.v] - Diff between revs 358 and 364

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Rev 358 Rev 364
Line 464... Line 464...
             `OR1200_EXCEPTFSM_IDLE:
             `OR1200_EXCEPTFSM_IDLE:
               if (except_flushpipe) begin
               if (except_flushpipe) begin
                  state <=  `OR1200_EXCEPTFSM_FLU1;
                  state <=  `OR1200_EXCEPTFSM_FLU1;
                  extend_flush <=  1'b1;
                  extend_flush <=  1'b1;
                  esr <=  sr_we ? to_sr : sr;
                  esr <=  sr_we ? to_sr : sr;
                  casex (except_trig)
                  casez (except_trig)
`ifdef OR1200_EXCEPT_ITLBMISS
`ifdef OR1200_EXCEPT_ITLBMISS
                    14'b1x_xxxx_xxxx_xxxx: begin
                    14'b1?_????_????_????: begin
                       except_type <=  `OR1200_EXCEPT_ITLBMISS;
                       except_type <=  `OR1200_EXCEPT_ITLBMISS;
                       eear <=  ex_dslot ?
                       eear <=  ex_dslot ?
                               ex_pc : ex_pc;
                               ex_pc : ex_pc;
                       epcr <=  ex_dslot ?
                       epcr <=  ex_dslot ?
                               wb_pc : ex_pc;
                               wb_pc : ex_pc;
                    end
                    end
`endif
`endif
`ifdef OR1200_EXCEPT_IPF
`ifdef OR1200_EXCEPT_IPF
                    14'b01_xxxx_xxxx_xxxx: begin
                    14'b01_????_????_????: begin
                       except_type <=  `OR1200_EXCEPT_IPF;
                       except_type <=  `OR1200_EXCEPT_IPF;
                       eear <=  ex_dslot ?
                       eear <=  ex_dslot ?
                               ex_pc : delayed1_ex_dslot ?
                               ex_pc : delayed1_ex_dslot ?
                               id_pc : delayed2_ex_dslot ?
                               id_pc : delayed2_ex_dslot ?
                               id_pc : id_pc;
                               id_pc : id_pc;
Line 488... Line 488...
                               id_pc : delayed2_ex_dslot ?
                               id_pc : delayed2_ex_dslot ?
                               id_pc : id_pc;
                               id_pc : id_pc;
                    end
                    end
`endif
`endif
`ifdef OR1200_EXCEPT_BUSERR
`ifdef OR1200_EXCEPT_BUSERR
                    14'b00_1xxx_xxxx_xxxx: begin        // Insn. Bus Error
                    14'b00_1???_????_????: begin        // Insn. Bus Error
                       except_type <=  `OR1200_EXCEPT_BUSERR;
                       except_type <=  `OR1200_EXCEPT_BUSERR;
                       eear <=  ex_dslot ?
                       eear <=  ex_dslot ?
                               wb_pc : ex_pc;
                               wb_pc : ex_pc;
                       epcr <=  ex_dslot ?
                       epcr <=  ex_dslot ?
                               wb_pc : ex_pc;
                               wb_pc : ex_pc;
                    end
                    end
`endif
`endif
`ifdef OR1200_EXCEPT_ILLEGAL
`ifdef OR1200_EXCEPT_ILLEGAL
                    14'b00_01xx_xxxx_xxxx: begin
                    14'b00_01??_????_????: begin
                       except_type <=  `OR1200_EXCEPT_ILLEGAL;
                       except_type <=  `OR1200_EXCEPT_ILLEGAL;
                       eear <=  ex_pc;
                       eear <=  ex_pc;
                       epcr <=  ex_dslot ?
                       epcr <=  ex_dslot ?
                               wb_pc : ex_pc;
                               wb_pc : ex_pc;
                    end
                    end
`endif
`endif
`ifdef OR1200_EXCEPT_ALIGN
`ifdef OR1200_EXCEPT_ALIGN
                    14'b00_001x_xxxx_xxxx: begin
                    14'b00_001?_????_????: begin
                       except_type <=  `OR1200_EXCEPT_ALIGN;
                       except_type <=  `OR1200_EXCEPT_ALIGN;
                       eear <=  lsu_addr;
                       eear <=  lsu_addr;
                       epcr <=  ex_dslot ?
                       epcr <=  ex_dslot ?
                               wb_pc : ex_pc;
                               wb_pc : ex_pc;
                    end
                    end
`endif
`endif
`ifdef OR1200_EXCEPT_DTLBMISS
`ifdef OR1200_EXCEPT_DTLBMISS
                    14'b00_0001_xxxx_xxxx: begin
                    14'b00_0001_????_????: begin
                       except_type <=  `OR1200_EXCEPT_DTLBMISS;
                       except_type <=  `OR1200_EXCEPT_DTLBMISS;
                       eear <=  lsu_addr;
                       eear <=  lsu_addr;
                       epcr <=  ex_dslot ?
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               dl_pc : ex_pc;
                               dl_pc : ex_pc;
                    end
                    end
`endif
`endif
`ifdef OR1200_EXCEPT_TRAP
`ifdef OR1200_EXCEPT_TRAP
                    14'b00_0000_1xxx_xxxx: begin
                    14'b00_0000_1???_????: begin
                       except_type <=  `OR1200_EXCEPT_TRAP;
                       except_type <=  `OR1200_EXCEPT_TRAP;
                       epcr <=  ex_dslot ?
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               id_pc : ex_pc;
                               id_pc : ex_pc;
                    end
                    end
`endif
`endif
`ifdef OR1200_EXCEPT_SYSCALL
`ifdef OR1200_EXCEPT_SYSCALL
                    14'b00_0000_01xx_xxxx: begin
                    14'b00_0000_01??_????: begin
                       except_type <=  `OR1200_EXCEPT_SYSCALL;
                       except_type <=  `OR1200_EXCEPT_SYSCALL;
                       epcr <=  ex_dslot ?
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               id_pc : delayed2_ex_dslot ?
                               id_pc : delayed2_ex_dslot ?
                               id_pc : id_pc;
                               id_pc : id_pc;
                    end
                    end
`endif
`endif
`ifdef OR1200_EXCEPT_DPF
`ifdef OR1200_EXCEPT_DPF
                    14'b00_0000_001x_xxxx: begin
                    14'b00_0000_001?_????: begin
                       except_type <=  `OR1200_EXCEPT_DPF;
                       except_type <=  `OR1200_EXCEPT_DPF;
                       eear <=  lsu_addr;
                       eear <=  lsu_addr;
                       epcr <=  ex_dslot ?
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               dl_pc : ex_pc;
                               dl_pc : ex_pc;
                    end
                    end
`endif
`endif
`ifdef OR1200_EXCEPT_BUSERR
`ifdef OR1200_EXCEPT_BUSERR
                    14'b00_0000_0001_xxxx: begin        // Data Bus Error
                    14'b00_0000_0001_????: begin        // Data Bus Error
                       except_type <=  `OR1200_EXCEPT_BUSERR;
                       except_type <=  `OR1200_EXCEPT_BUSERR;
                       eear <=  lsu_addr;
                       eear <=  lsu_addr;
                       epcr <=  ex_dslot ?
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               dl_pc : ex_pc;
                               dl_pc : ex_pc;
                    end
                    end
`endif
`endif
`ifdef OR1200_EXCEPT_RANGE
`ifdef OR1200_EXCEPT_RANGE
                    14'b00_0000_0000_1xxx: begin
                    14'b00_0000_0000_1???: begin
                       except_type <=  `OR1200_EXCEPT_RANGE;
                       except_type <=  `OR1200_EXCEPT_RANGE;
                       epcr <=  ex_dslot ?
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               id_pc : delayed2_ex_dslot ?
                               id_pc : delayed2_ex_dslot ?
                               id_pc : id_pc;
                               id_pc : id_pc;
                    end
                    end
`endif
`endif
`ifdef OR1200_EXCEPT_FLOAT
`ifdef OR1200_EXCEPT_FLOAT
                    14'b00_0000_0000_01xx: begin
                    14'b00_0000_0000_01??: begin
                       except_type <=  `OR1200_EXCEPT_FLOAT;
                       except_type <=  `OR1200_EXCEPT_FLOAT;
                       epcr <=  id_pc;
                       epcr <=  id_pc;
                    end
                    end
`endif
`endif
`ifdef OR1200_EXCEPT_INT
`ifdef OR1200_EXCEPT_INT
                    14'b00_0000_0000_001x: begin
                    14'b00_0000_0000_001?: begin
                       except_type <=  `OR1200_EXCEPT_INT;
                       except_type <=  `OR1200_EXCEPT_INT;
                       epcr <=  id_pc;
                       epcr <=  id_pc;
                    end
                    end
`endif
`endif
`ifdef OR1200_EXCEPT_TICK
`ifdef OR1200_EXCEPT_TICK

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