URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_fpu.v] - Diff between revs 258 and 260

Rev 258	Rev 260
Line 280...	Line 280...

`//`	`//`
`// Instantiate FPU modules`	`// Instantiate FPU modules`
`//`	`//`

`ifdef OR1200_FPU_ARITH_FPU100

`// FPU 100 VHDL core from OpenCores.org: http://opencores.org/project,fpu100`	`// FPU 100 VHDL core from OpenCores.org: http://opencores.org/project,fpu100`
`// Used only for add,sub,mul,div`	`// Used only for add,sub,mul,div`
`or1200_fpu_arith fpu_arith`	`or1200_fpu_arith fpu_arith`
`(`	`(`
`.clk_i(clk),`	`.clk_i(clk),`
Line 304...	Line 302...
`.zero_o(zero),`	`.zero_o(zero),`
`.qnan_o(qnan),`	`.qnan_o(qnan),`
`.snan_o(snan)`	`.snan_o(snan)`
`);`	`);`

`endif // `ifdef OR1200_FPU_ARITH_FPU100

`// Logic for detection of signaling NaN on input`	`// Logic for detection of signaling NaN on input`
`// signaling NaN: exponent is 8hff, [22] is zero, rest of fract is non-zero`	`// signaling NaN: exponent is 8hff, [22] is zero, rest of fract is non-zero`
`// quiet NaN: exponent is 8hff, [22] is 1`	`// quiet NaN: exponent is 8hff, [22] is 1`
`reg a_is_snan, b_is_snan;`	`reg a_is_snan, b_is_snan;`
`reg a_is_qnan, b_is_qnan;`	`reg a_is_qnan, b_is_qnan;`