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output_zero_fasu ;
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output_zero_fasu ;
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assign inv = inv_d & !f2i_special_case_no_inv;
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assign inv = inv_d & !f2i_special_case_no_inv;
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endmodule // or1200_fpu_intfloat_conv
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endmodule // or1200_fpu_intfloat_conv
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module or1200_fpu_intfloat_conv_except
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(
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clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan,
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opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn
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);
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input clk;
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input [31:0] opa, opb;
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output inf, ind, qnan, snan, opa_nan, opb_nan;
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output opa_00, opb_00;
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output opa_inf, opb_inf;
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output opa_dn;
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output opb_dn;
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////////////////////////////////////////////////////////////////////////
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//
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// Local Wires and registers
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//
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wire [7:0] expa, expb; // alias to opX exponent
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wire [22:0] fracta, fractb; // alias to opX fraction
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reg expa_ff, infa_f_r, qnan_r_a, snan_r_a;
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reg expb_ff, infb_f_r, qnan_r_b, snan_r_b;
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reg inf, ind, qnan, snan; // Output registers
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reg opa_nan, opb_nan;
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reg expa_00, expb_00, fracta_00, fractb_00;
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reg opa_00, opb_00;
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reg opa_inf, opb_inf;
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reg opa_dn, opb_dn;
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////////////////////////////////////////////////////////////////////////
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//
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// Aliases
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//
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assign expa = opa[30:23];
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assign expb = opb[30:23];
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assign fracta = opa[22:0];
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assign fractb = opb[22:0];
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////////////////////////////////////////////////////////////////////////
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//
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// Determine if any of the input operators is a INF or NAN or any other
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// special number
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//
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always @(posedge clk)
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expa_ff <= &expa;
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always @(posedge clk)
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expb_ff <= &expb;
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always @(posedge clk)
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infa_f_r <= !(|fracta);
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always @(posedge clk)
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infb_f_r <= !(|fractb);
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always @(posedge clk)
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qnan_r_a <= fracta[22];
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always @(posedge clk)
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snan_r_a <= !fracta[22] & |fracta[21:0];
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always @(posedge clk)
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qnan_r_b <= fractb[22];
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always @(posedge clk)
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snan_r_b <= !fractb[22]; // & |fractb[21:0];
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always @(posedge clk)
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ind <= (expa_ff & infa_f_r); // & (expb_ff & infb_f_r);
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always @(posedge clk)
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inf <= (expa_ff & infa_f_r); // | (expb_ff & infb_f_r);
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always @(posedge clk)
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qnan <= (expa_ff & qnan_r_a); // | (expb_ff & qnan_r_b);
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always @(posedge clk)
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snan <= (expa_ff & snan_r_a); // | (expb_ff & snan_r_b);
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always @(posedge clk)
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opa_nan <= &expa & (|fracta[22:0]);
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always @(posedge clk)
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opb_nan <= &expb & (|fractb[22:0]);
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always @(posedge clk)
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opa_inf <= (expa_ff & infa_f_r);
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always @(posedge clk)
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opb_inf <= (expb_ff & infb_f_r);
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always @(posedge clk)
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expa_00 <= !(|expa);
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always @(posedge clk)
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expb_00 <= !(|expb);
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always @(posedge clk)
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fracta_00 <= !(|fracta);
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always @(posedge clk)
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fractb_00 <= !(|fractb);
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always @(posedge clk)
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opa_00 <= expa_00 & fracta_00;
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always @(posedge clk)
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opb_00 <= expb_00 & fractb_00;
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always @(posedge clk)
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opa_dn <= expa_00;
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always @(posedge clk)
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opb_dn <= expb_00;
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endmodule // or1200_fpu_intfloat_conv_except
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No newline at end of file
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No newline at end of file
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