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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_fpu_post_norm_addsub.v] - Diff between revs 258 and 364

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Rev 258 Rev 364
Line 130... Line 130...
   assign s_carry = s_fract_28_i[27];
   assign s_carry = s_fract_28_i[27];
 
 
   reg [5:0] lzeroes;
   reg [5:0] lzeroes;
 
 
   always @(s_fract_28_i)
   always @(s_fract_28_i)
     casex(s_fract_28_i[26:0])   // synopsys full_case parallel_case
     casez(s_fract_28_i[26:0])   // synopsys full_case parallel_case
       27'b1??????????????????????????: lzeroes <=  0;
       27'b1??????????????????????????: lzeroes = 0;
       27'b01?????????????????????????: lzeroes <=  1;
       27'b01?????????????????????????: lzeroes = 1;
       27'b001????????????????????????: lzeroes <=  2;
       27'b001????????????????????????: lzeroes = 2;
       27'b0001???????????????????????: lzeroes <=  3;
       27'b0001???????????????????????: lzeroes = 3;
       27'b00001??????????????????????: lzeroes <=  4;
       27'b00001??????????????????????: lzeroes = 4;
       27'b000001?????????????????????: lzeroes <=  5;
       27'b000001?????????????????????: lzeroes = 5;
       27'b0000001????????????????????: lzeroes <=  6;
       27'b0000001????????????????????: lzeroes = 6;
       27'b00000001???????????????????: lzeroes <=  7;
       27'b00000001???????????????????: lzeroes = 7;
       27'b000000001??????????????????: lzeroes <=  8;
       27'b000000001??????????????????: lzeroes = 8;
       27'b0000000001?????????????????: lzeroes <=  9;
       27'b0000000001?????????????????: lzeroes = 9;
       27'b00000000001????????????????: lzeroes <=  10;
       27'b00000000001????????????????: lzeroes = 10;
       27'b000000000001???????????????: lzeroes <=  11;
       27'b000000000001???????????????: lzeroes = 11;
       27'b0000000000001??????????????: lzeroes <=  12;
       27'b0000000000001??????????????: lzeroes = 12;
       27'b00000000000001?????????????: lzeroes <=  13;
       27'b00000000000001?????????????: lzeroes = 13;
       27'b000000000000001????????????: lzeroes <=  14;
       27'b000000000000001????????????: lzeroes = 14;
       27'b0000000000000001???????????: lzeroes <=  15;
       27'b0000000000000001???????????: lzeroes = 15;
       27'b00000000000000001??????????: lzeroes <=  16;
       27'b00000000000000001??????????: lzeroes = 16;
       27'b000000000000000001?????????: lzeroes <=  17;
       27'b000000000000000001?????????: lzeroes = 17;
       27'b0000000000000000001????????: lzeroes <=  18;
       27'b0000000000000000001????????: lzeroes = 18;
       27'b00000000000000000001???????: lzeroes <=  19;
       27'b00000000000000000001???????: lzeroes = 19;
       27'b000000000000000000001??????: lzeroes <=  20;
       27'b000000000000000000001??????: lzeroes = 20;
       27'b0000000000000000000001?????: lzeroes <=  21;
       27'b0000000000000000000001?????: lzeroes = 21;
       27'b00000000000000000000001????: lzeroes <=  22;
       27'b00000000000000000000001????: lzeroes = 22;
       27'b000000000000000000000001???: lzeroes <=  23;
       27'b000000000000000000000001???: lzeroes = 23;
       27'b0000000000000000000000001??: lzeroes <=  24;
       27'b0000000000000000000000001??: lzeroes = 24;
       27'b00000000000000000000000001?: lzeroes <=  25;
       27'b00000000000000000000000001?: lzeroes = 25;
       27'b000000000000000000000000001: lzeroes <=  26;
       27'b000000000000000000000000001: lzeroes = 26;
       27'b000000000000000000000000000: lzeroes <=  27;
       27'b000000000000000000000000000: lzeroes = 27;
     endcase
     endcase
 
 
   assign s_zeros = s_fract_28_i[27] ? 0 : lzeroes;
   assign s_zeros = s_fract_28_i[27] ? 0 : lzeroes;
 
 
   // negative flag & large flag & exp          
   // negative flag & large flag & exp          

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