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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_fpu_post_norm_intfloat_conv.v] - Diff between revs 258 and 364

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Rev 258 Rev 364
Line 135... Line 135...
 
 
   // ---------------------------------------------------------------------
   // ---------------------------------------------------------------------
   // Count Leading zeros in fraction
   // Count Leading zeros in fraction
 
 
   always @(/*fract_in*/ posedge clk)
   always @(/*fract_in*/ posedge clk)
     casex(fract_in)    // synopsys full_case parallel_case
     casez(fract_in)    // synopsys full_case parallel_case
       48'b1???????????????????????????????????????????????: fi_ldz <=  1;
       48'b1???????????????????????????????????????????????: fi_ldz <=  1;
       48'b01??????????????????????????????????????????????: fi_ldz <=  2;
       48'b01??????????????????????????????????????????????: fi_ldz <=  2;
       48'b001?????????????????????????????????????????????: fi_ldz <=  3;
       48'b001?????????????????????????????????????????????: fi_ldz <=  3;
       48'b0001????????????????????????????????????????????: fi_ldz <=  4;
       48'b0001????????????????????????????????????????????: fi_ldz <=  4;
       48'b00001???????????????????????????????????????????: fi_ldz <=  5;
       48'b00001???????????????????????????????????????????: fi_ldz <=  5;
Line 292... Line 292...
   assign exp_out_mi1   = exp_out - 1;
   assign exp_out_mi1   = exp_out - 1;
   assign exp_in_pl1    = exp_in  + 1;  // 9 bits - includes carry out
   assign exp_in_pl1    = exp_in  + 1;  // 9 bits - includes carry out
   assign exp_in_mi1    = exp_in  - 1;  // 9 bits - includes carry out
   assign exp_in_mi1    = exp_in  - 1;  // 9 bits - includes carry out
   assign exp_out1_mi1  = exp_out1 - 1;
   assign exp_out1_mi1  = exp_out1 - 1;
 
 
   assign exp_next_mi  = exp_in_pl1 - fi_ldz_mi1; // 9 bits - includes carry out
   assign exp_next_mi  = exp_in_pl1 -
 
                         {3'd0,fi_ldz_mi1}; // 9 bits - includes carry out
 
 
   assign {exp_out1_co, exp_out1} = fract_in[47] ? exp_in_pl1 : exp_next_mi;
   assign {exp_out1_co, exp_out1} = fract_in[47] ? exp_in_pl1 : exp_next_mi;
 
 
   // Only ever force positive if:
   // Only ever force positive if:
   // i) It's a NaN
   // i) It's a NaN
Line 307... Line 308...
                         1 : opa_nan | (f2i_zero & !f2i_max & !(opa_inf & opas))
                         1 : opa_nan | (f2i_zero & !f2i_max & !(opa_inf & opas))
                           | (!(|out) & !f2i_zero)
                           | (!(|out) & !f2i_zero)
                             ?
                             ?
                         0 :opas;
                         0 :opas;
 
 
   assign exp_i2f   = fract_in_00 ? (opas ? 8'h9e : 0) : (8'h9e-fi_ldz);
   assign exp_i2f   = fract_in_00 ? (opas ? 8'h9e : 0) : (8'h9e-{2'd0,fi_ldz});
   assign exp_f2i_1 = {{8{fract_in[47]}}, fract_in }<<f2i_shft;
   assign exp_f2i_1 = {{8{fract_in[47]}}, fract_in }<<f2i_shft;
   assign exp_f2i   = f2i_zero ? 0 : f2i_max ? 8'hff : exp_f2i_1[55:48];
   assign exp_f2i   = f2i_zero ? 0 : f2i_max ? 8'hff : exp_f2i_1[55:48];
   assign conv_exp  = op_f2i ? exp_f2i : exp_i2f;
   assign conv_exp  = op_f2i ? exp_f2i : exp_i2f;
 
 
   //assign exp_out = conv_exp;
   //assign exp_out = conv_exp;
   always @(posedge clk)
   always @(posedge clk)
     exp_out <= conv_exp;
     exp_out <= conv_exp;
 
 
 
 
   assign ldz_all   = fi_ldz;
   assign ldz_all   = {1'b0,fi_ldz};
   assign fi_ldz_2a = 6'd23 - fi_ldz;
   assign fi_ldz_2a = 6'd23 - fi_ldz;
   assign fi_ldz_2  = {fi_ldz_2a[6], fi_ldz_2a[6:0]};
   assign fi_ldz_2  = {fi_ldz_2a[6], fi_ldz_2a[6:0]};
 
 
 
 
   // ---------------------------------------------------------------------
   // ---------------------------------------------------------------------

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