URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_genpc.v] - Diff between revs 847 and 852

Rev 847	Rev 852
Line 263...	Line 263...
`ex_branch_taken = 1'b0;`	`ex_branch_taken = 1'b0;`
`end`	`end`
`endcase`	`endcase`
`end`	`end`

	`// select async. value for pcreg after reset - PC jumps to the address selected`
	`// after boot.`
	`wire [31:0] pcreg_boot = boot_adr;`

`//`	`//`
`// PC register`	`// PC register`
`//`	`//`
always @(posedge clk or `OR1200_RST_EVENT rst)	always @(posedge clk or `OR1200_RST_EVENT rst)
`// default value`	`// default value`
Line 287...	Line 291...
`else if (no_more_dslot \| except_start \| !genpc_freeze & !icpu_rty_i`	`else if (no_more_dslot \| except_start \| !genpc_freeze & !icpu_rty_i`
`& !genpc_refetch) begin`	`& !genpc_refetch) begin`
`pcreg_default <= pc[31:2];`	`pcreg_default <= pc[31:2];`
`end`	`end`

`// select async. value for pcreg after reset - PC jumps to the address selected`
`// after boot.`
`wire [31:0] pcreg_boot = boot_adr;`

`always @(pcreg_boot or pcreg_default or pcreg_select)`	`always @(pcreg_boot or pcreg_default or pcreg_select)`
`if (pcreg_select)`	`if (pcreg_select)`
`// async. value is selected due to reset state`	`// async. value is selected due to reset state`
`pcreg = pcreg_boot[31:2];`	`pcreg = pcreg_boot[31:2];`
`else`	`else`