| Line 62... |
Line 62... |
// Internal i/f
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// Internal i/f
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pre_branch_op, branch_op, except_type, except_prefix,
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pre_branch_op, branch_op, except_type, except_prefix,
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id_branch_addrtarget, ex_branch_addrtarget, muxed_b, operand_b,
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id_branch_addrtarget, ex_branch_addrtarget, muxed_b, operand_b,
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flag, flagforw, ex_branch_taken, except_start,
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flag, flagforw, ex_branch_taken, except_start,
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epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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genpc_freeze, no_more_dslot, lsu_stall
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genpc_freeze, no_more_dslot, lsu_stall, du_flush_pipe, spr_dat_npc
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);
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);
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|
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//
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//
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// I/O
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// I/O
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//
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//
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| Line 103... |
Line 103... |
output ex_branch_taken;
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output ex_branch_taken;
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input except_start;
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input except_start;
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input [31:0] epcr;
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input [31:0] epcr;
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input [31:0] spr_dat_i;
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input [31:0] spr_dat_i;
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input spr_pc_we;
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input spr_pc_we;
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input [31:0] spr_dat_npc;
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input genpc_refetch;
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input genpc_refetch;
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input genpc_freeze;
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input genpc_freeze;
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input no_more_dslot;
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input no_more_dslot;
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input lsu_stall;
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input lsu_stall;
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input du_flush_pipe;
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parameter boot_adr = `OR1200_BOOT_ADR;
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parameter boot_adr = `OR1200_BOOT_ADR;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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| Line 124... |
Line 126... |
reg wait_lsu;
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reg wait_lsu;
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//
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//
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// Address of insn to be fecthed
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// Address of insn to be fecthed
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//
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//
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assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we
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assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & !du_flush_pipe
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& (icpu_rty_i | genpc_refetch) ?
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& (icpu_rty_i | genpc_refetch) ?
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icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};
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icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};
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|
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//
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//
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// Control access to IC subsystem
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// Control access to IC subsystem
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| Line 163... |
Line 165... |
// Async calculation of new PC value. This value is used for addressing the
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// Async calculation of new PC value. This value is used for addressing the
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// IC.
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// IC.
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//
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//
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always @(pcreg or ex_branch_addrtarget or flag or branch_op or except_type
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always @(pcreg or ex_branch_addrtarget or flag or branch_op or except_type
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or except_start or operand_b or epcr or spr_pc_we or spr_dat_i or
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or except_start or operand_b or epcr or spr_pc_we or spr_dat_i or
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except_prefix)
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except_prefix or du_flush_pipe)
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begin
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begin
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casez ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
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casez ({du_flush_pipe, spr_pc_we, except_start, branch_op}) // synopsys parallel_case
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{2'b00, `OR1200_BRANCHOP_NOP}: begin
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{3'b000, `OR1200_BRANCHOP_NOP}: begin
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pc = {pcreg + 30'd1, 2'b0};
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pc = {pcreg + 30'd1, 2'b0};
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ex_branch_taken = 1'b0;
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ex_branch_taken = 1'b0;
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end
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end
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{2'b00, `OR1200_BRANCHOP_J}: begin
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{3'b000, `OR1200_BRANCHOP_J}: begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: BRANCHOP_J: pc <= ex_branch_addrtarget %h"
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$display("%t: BRANCHOP_J: pc <= ex_branch_addrtarget %h"
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, $time, ex_branch_addrtarget);
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, $time, ex_branch_addrtarget);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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pc = {ex_branch_addrtarget, 2'b00};
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pc = {ex_branch_addrtarget, 2'b00};
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ex_branch_taken = 1'b1;
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ex_branch_taken = 1'b1;
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end
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end
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{2'b00, `OR1200_BRANCHOP_JR}: begin
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{3'b000, `OR1200_BRANCHOP_JR}: begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: BRANCHOP_JR: pc <= operand_b %h",
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$display("%t: BRANCHOP_JR: pc <= operand_b %h",
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$time, operand_b);
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$time, operand_b);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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pc = operand_b;
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pc = operand_b;
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ex_branch_taken = 1'b1;
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ex_branch_taken = 1'b1;
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end
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end
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{2'b00, `OR1200_BRANCHOP_BF}:
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{3'b000, `OR1200_BRANCHOP_BF}:
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if (flag) begin
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if (flag) begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: BRANCHOP_BF: pc <= ex_branch_addrtarget %h",
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$display("%t: BRANCHOP_BF: pc <= ex_branch_addrtarget %h",
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$time, ex_branch_addrtarget);
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$time, ex_branch_addrtarget);
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| Line 210... |
Line 212... |
// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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pc = {pcreg + 30'd1, 2'b0};
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pc = {pcreg + 30'd1, 2'b0};
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ex_branch_taken = 1'b0;
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ex_branch_taken = 1'b0;
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end
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end
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{2'b00, `OR1200_BRANCHOP_BNF}:
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{3'b000, `OR1200_BRANCHOP_BNF}:
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if (flag) begin
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if (flag) begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: BRANCHOP_BNF: not taken", $time);
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$display("%t: BRANCHOP_BNF: not taken", $time);
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// synopsys translate_on
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// synopsys translate_on
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| Line 230... |
Line 232... |
// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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pc = {ex_branch_addrtarget, 2'b00};
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pc = {ex_branch_addrtarget, 2'b00};
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ex_branch_taken = 1'b1;
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ex_branch_taken = 1'b1;
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end
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end
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{2'b00, `OR1200_BRANCHOP_RFE}: begin
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{3'b000, `OR1200_BRANCHOP_RFE}: begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: BRANCHOP_RFE: pc <= epcr %h",
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$display("%t: BRANCHOP_RFE: pc <= epcr %h",
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$time, epcr);
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$time, epcr);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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pc = epcr;
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pc = epcr;
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ex_branch_taken = 1'b1;
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ex_branch_taken = 1'b1;
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end
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end
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{2'b01, 3'b???}: begin
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{3'b100, 3'b???}: begin
|
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`ifdef OR1200_VERBOSE
|
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// synopsys translate_off
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$display("Reload breaked ins at : %h.", spr_dat_npc);
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// synopsys translate_on
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`endif
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pc = spr_dat_npc;
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ex_branch_taken = 1'b1;
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end
|
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{3'b001, 3'b???}: begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("Starting exception: %h.", except_type);
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$display("Starting exception: %h.", except_type);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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| Line 286... |
Line 297... |
pcreg_select <= 1'b0; // select FF value
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pcreg_select <= 1'b0; // select FF value
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end
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end
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else if (spr_pc_we) begin
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else if (spr_pc_we) begin
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pcreg_default <= spr_dat_i[31:2];
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pcreg_default <= spr_dat_i[31:2];
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end
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end
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else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i
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else if (du_flush_pipe | no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i
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& !genpc_refetch) begin
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& !genpc_refetch) begin
|
pcreg_default <= pc[31:2];
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pcreg_default <= pc[31:2];
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end
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end
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always @(pcreg_boot or pcreg_default or pcreg_select)
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always @(pcreg_boot or pcreg_default or pcreg_select)
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