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Line 41... |
//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: or1200_genpc.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Structure reordered and bugs fixed.
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//
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// Revision 1.10 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.9 2004/04/05 08:29:57 lampret
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// Revision 1.9 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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// Merged branch_qmem into main tree.
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//
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//
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// Revision 1.7.4.3 2003/12/17 13:43:38 simons
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// Revision 1.7.4.3 2003/12/17 13:43:38 simons
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// Exception prefix configuration changed.
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// Exception prefix configuration changed.
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| Line 112... |
Line 119... |
// External i/f to IC
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// External i/f to IC
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icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
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icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
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icpu_rty_i, icpu_adr_i,
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icpu_rty_i, icpu_adr_i,
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// Internal i/f
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// Internal i/f
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branch_op, except_type, except_prefix,
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pre_branch_op, branch_op, except_type, except_prefix,
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branch_addrofs, lr_restor, flag, taken, except_start,
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id_branch_addrtarget, ex_branch_addrtarget, muxed_b, operand_b,
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binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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flag, flagforw, ex_branch_taken, except_start,
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genpc_freeze, genpc_stop_prefetch, no_more_dslot
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epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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genpc_freeze, no_more_dslot
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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| Line 141... |
Line 149... |
input [31:0] icpu_adr_i;
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input [31:0] icpu_adr_i;
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//
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//
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// Internal i/f
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// Internal i/f
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//
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//
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input [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op;
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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input except_prefix;
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input except_prefix;
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input [31:2] branch_addrofs;
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input [31:2] id_branch_addrtarget;
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input [31:0] lr_restor;
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input [31:2] ex_branch_addrtarget;
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input [31:0] muxed_b;
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input [31:0] operand_b;
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input flag;
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input flag;
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output taken;
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input flagforw;
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output ex_branch_taken;
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input except_start;
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input except_start;
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input [31:2] binsn_addr;
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input [31:0] epcr;
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input [31:0] epcr;
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input [31:0] spr_dat_i;
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input [31:0] spr_dat_i;
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input spr_pc_we;
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input spr_pc_we;
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input genpc_refetch;
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input genpc_refetch;
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input genpc_stop_prefetch;
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input genpc_freeze;
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input genpc_freeze;
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input no_more_dslot;
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input no_more_dslot;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [31:2] pcreg_default;
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wire [31:0] pcreg_boot;
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reg pcreg_select;
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reg [31:2] pcreg;
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reg [31:2] pcreg;
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reg [31:0] pc;
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reg [31:0] pc;
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reg taken; /* Set to in case of jump or taken branch */
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reg ex_branch_taken; /* Set to in case of jump or taken branch */
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reg genpc_refetch_r;
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reg genpc_refetch_r;
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//
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//
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// Address of insn to be fecthed
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// Address of insn to be fecthed
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//
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//
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assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
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assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};
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// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
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//
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//
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// Control access to IC subsystem
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// Control access to IC subsystem
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//
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//
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// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;
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assign icpu_cycstb_o = ~(genpc_freeze | (|pre_branch_op && !icpu_rty_i));
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assign icpu_cycstb_o = !genpc_freeze; // works, except remaining raised cycstb during long load/store
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//assign icpu_cycstb_o = !(genpc_freeze | genpc_refetch & genpc_refetch_r);
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//assign icpu_cycstb_o = !(genpc_freeze | genpc_stop_prefetch);
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assign icpu_sel_o = 4'b1111;
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assign icpu_sel_o = 4'b1111;
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assign icpu_tag_o = `OR1200_ITAG_NI;
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assign icpu_tag_o = `OR1200_ITAG_NI;
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//
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//
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// genpc_freeze_r
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// genpc_freeze_r
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| Line 196... |
Line 205... |
genpc_refetch_r <= #1 1'b0;
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genpc_refetch_r <= #1 1'b0;
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//
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//
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// Async calculation of new PC value. This value is used for addressing the IC.
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// Async calculation of new PC value. This value is used for addressing the IC.
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//
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//
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always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
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always @(pcreg or ex_branch_addrtarget or flag or branch_op or except_type
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or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
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or except_start or operand_b or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
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casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
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casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
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{2'b00, `OR1200_BRANCHOP_NOP}: begin
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{2'b00, `OR1200_BRANCHOP_NOP}: begin
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pc = {pcreg + 30'd1, 2'b0};
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pc = {pcreg + 30'd1, 2'b0};
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taken = 1'b0;
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ex_branch_taken = 1'b0;
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end
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end
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{2'b00, `OR1200_BRANCHOP_J}: begin
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{2'b00, `OR1200_BRANCHOP_J}: begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);
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$display("%t: BRANCHOP_J: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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pc = {branch_addrofs, 2'b0};
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pc = {ex_branch_addrtarget, 2'b00};
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taken = 1'b1;
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ex_branch_taken = 1'b1;
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end
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end
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{2'b00, `OR1200_BRANCHOP_JR}: begin
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{2'b00, `OR1200_BRANCHOP_JR}: begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);
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$display("%t: BRANCHOP_JR: pc <= operand_b %h", $time, operand_b);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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pc = lr_restor;
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pc = operand_b;
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taken = 1'b1;
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ex_branch_taken = 1'b1;
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end
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{2'b00, `OR1200_BRANCHOP_BAL}: begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
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// synopsys translate_on
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`endif
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pc = {binsn_addr + branch_addrofs, 2'b0};
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taken = 1'b1;
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end
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end
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{2'b00, `OR1200_BRANCHOP_BF}:
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{2'b00, `OR1200_BRANCHOP_BF}:
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if (flag) begin
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if (flag) begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
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$display("%t: BRANCHOP_BF: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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pc = {binsn_addr + branch_addrofs, 2'b0};
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pc = {ex_branch_addrtarget, 2'b00};
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taken = 1'b1;
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ex_branch_taken = 1'b1;
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end
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end
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else begin
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else begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: BRANCHOP_BF: not taken", $time);
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$display("%t: BRANCHOP_BF: not taken", $time);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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pc = {pcreg + 30'd1, 2'b0};
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pc = {pcreg + 30'd1, 2'b0};
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taken = 1'b0;
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ex_branch_taken = 1'b0;
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end
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end
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{2'b00, `OR1200_BRANCHOP_BNF}:
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{2'b00, `OR1200_BRANCHOP_BNF}:
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if (flag) begin
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if (flag) begin
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pc = {pcreg + 30'd1, 2'b0};
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: BRANCHOP_BNF: not taken", $time);
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$display("%t: BRANCHOP_BNF: not taken", $time);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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taken = 1'b0;
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pc = {pcreg + 30'd1, 2'b0};
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ex_branch_taken = 1'b0;
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end
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end
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else begin
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else begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
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$display("%t: BRANCHOP_BNF: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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pc = {binsn_addr + branch_addrofs, 2'b0};
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pc = {ex_branch_addrtarget, 2'b00};
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taken = 1'b1;
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ex_branch_taken = 1'b1;
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end
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end
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{2'b00, `OR1200_BRANCHOP_RFE}: begin
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{2'b00, `OR1200_BRANCHOP_RFE}: begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
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$display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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pc = epcr;
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pc = epcr;
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taken = 1'b1;
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ex_branch_taken = 1'b1;
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end
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end
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{2'b01, 3'bxxx}: begin
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{2'b01, 3'bxxx}: begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("Starting exception: %h.", except_type);
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$display("Starting exception: %h.", except_type);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V};
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pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V};
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taken = 1'b1;
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ex_branch_taken = 1'b1;
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end
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end
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default: begin
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default: begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("l.mtspr writing into PC: %h.", spr_dat_i);
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$display("l.mtspr writing into PC: %h.", spr_dat_i);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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pc = spr_dat_i;
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pc = spr_dat_i;
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taken = 1'b0;
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ex_branch_taken = 1'b0;
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end
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end
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endcase
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endcase
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end
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end
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//
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//
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// PC register
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// PC register
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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// default value
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// pcreg <= #1 30'd63;
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if (rst) begin
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pcreg <= #1 ({(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1) >> 2;
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//pcreg_default <= #1 30'd63;
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else if (spr_pc_we)
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pcreg_default <= #1 /*30'd63 */ `OR1200_BOOT_PCREG_DEFAULT; // jb
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pcreg <= #1 spr_dat_i[31:2];
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pcreg_select <= #1 1'b1; // select async. value due to reset state
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else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
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end
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// else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
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// selected value (different from default) is written into FF after reset state
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pcreg <= #1 pc[31:2];
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else if (pcreg_select) begin
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pcreg_default <= #1 pcreg_boot[31:2]; // dynamic value can only be assigned to FF out of reset!
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pcreg_select <= #1 1'b0; // select FF value
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end
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else if (spr_pc_we) begin
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pcreg_default <= #1 spr_dat_i[31:2];
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end
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else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch) begin
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pcreg_default <= #1 pc[31:2];
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end
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// select async. value for pcreg after reset - PC jumps to the address selected after boot!
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//assign pcreg_boot = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1;
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assign pcreg_boot = `OR1200_BOOT_ADR; // changed JB
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always @(pcreg_boot or pcreg_default or pcreg_select)
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if (pcreg_select)
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pcreg = pcreg_boot[31:2]; // async. value is selected due to reset state
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else
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pcreg = pcreg_default ; // FF value is selected 2nd clock after reset state
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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