| Line 1... |
Line 1... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// OR1200's generate PC ////
|
//// OR1200's generate PC ////
|
//// ////
|
//// ////
|
//// This file is part of the OpenRISC 1200 project ////
|
//// This file is part of the OpenRISC 1200 project ////
|
//// http://www.opencores.org/cores/or1k/ ////
|
//// http://www.opencores.org/project,or1k ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// PC, interface to IC. ////
|
//// PC, interface to IC. ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
| Line 39... |
Line 39... |
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
|
//
|
|
// $Log: or1200_genpc.v,v $
|
// $Log: or1200_genpc.v,v $
|
// Revision 2.0 2010/06/30 11:00:00 ORSoC
|
// Revision 2.0 2010/06/30 11:00:00 ORSoC
|
// Major update:
|
// Major update:
|
// Structure reordered and bugs fixed.
|
// Structure reordered and bugs fixed.
|
//
|
|
// Revision 1.10 2004/06/08 18:17:36 lampret
|
|
// Non-functional changes. Coding style fixes.
|
|
//
|
|
// Revision 1.9 2004/04/05 08:29:57 lampret
|
|
// Merged branch_qmem into main tree.
|
|
//
|
|
// Revision 1.7.4.3 2003/12/17 13:43:38 simons
|
|
// Exception prefix configuration changed.
|
|
//
|
|
// Revision 1.7.4.2 2003/12/04 23:44:31 lampret
|
|
// Static exception prefix.
|
|
//
|
|
// Revision 1.7.4.1 2003/07/08 15:36:37 lampret
|
|
// Added embedded memory QMEM.
|
|
//
|
|
// Revision 1.7 2003/04/20 22:23:57 lampret
|
|
// No functional change. Only added customization for exception vectors.
|
|
//
|
|
// Revision 1.6 2002/03/29 15:16:55 lampret
|
|
// Some of the warnings fixed.
|
|
//
|
|
// Revision 1.5 2002/02/11 04:33:17 lampret
|
|
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
|
|
//
|
|
// Revision 1.4 2002/01/28 01:16:00 lampret
|
|
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
|
|
//
|
|
// Revision 1.3 2002/01/18 07:56:00 lampret
|
|
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
|
|
//
|
|
// Revision 1.2 2002/01/14 06:18:22 lampret
|
|
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
|
|
//
|
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
|
//
|
|
// Revision 1.10 2001/11/20 18:46:15 simons
|
|
// Break point bug fixed
|
|
//
|
|
// Revision 1.9 2001/11/18 09:58:28 lampret
|
|
// Fixed some l.trap typos.
|
|
//
|
|
// Revision 1.8 2001/11/18 08:36:28 lampret
|
|
// For GDB changed single stepping and disabled trap exception.
|
|
//
|
|
// Revision 1.7 2001/10/21 17:57:16 lampret
|
|
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
|
|
//
|
|
// Revision 1.6 2001/10/14 13:12:09 lampret
|
|
// MP3 version.
|
|
//
|
|
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
|
|
// no message
|
|
//
|
|
// Revision 1.1 2001/08/09 13:39:33 lampret
|
|
// Major clean-up.
|
|
//
|
|
//
|
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
`include "or1200_defines.v"
|
`include "or1200_defines.v"
|
| Line 176... |
Line 115... |
reg [31:2] pcreg_default;
|
reg [31:2] pcreg_default;
|
wire [31:0] pcreg_boot;
|
wire [31:0] pcreg_boot;
|
reg pcreg_select;
|
reg pcreg_select;
|
reg [31:2] pcreg;
|
reg [31:2] pcreg;
|
reg [31:0] pc;
|
reg [31:0] pc;
|
reg ex_branch_taken; /* Set to in case of jump or taken branch */
|
// Set in event of jump or taken branch
|
|
reg ex_branch_taken;
|
reg genpc_refetch_r;
|
reg genpc_refetch_r;
|
|
|
//
|
//
|
// Address of insn to be fecthed
|
// Address of insn to be fecthed
|
//
|
//
|
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};
|
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we
|
|
& (icpu_rty_i | genpc_refetch) ?
|
|
icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};
|
|
|
//
|
//
|
// Control access to IC subsystem
|
// Control access to IC subsystem
|
//
|
//
|
assign icpu_cycstb_o = ~(genpc_freeze | (|pre_branch_op && !icpu_rty_i));
|
assign icpu_cycstb_o = ~(genpc_freeze | (|pre_branch_op && !icpu_rty_i));
|
| Line 203... |
Line 145... |
genpc_refetch_r <= #1 1'b1;
|
genpc_refetch_r <= #1 1'b1;
|
else
|
else
|
genpc_refetch_r <= #1 1'b0;
|
genpc_refetch_r <= #1 1'b0;
|
|
|
//
|
//
|
// Async calculation of new PC value. This value is used for addressing the IC.
|
// Async calculation of new PC value. This value is used for addressing the
|
|
// IC.
|
//
|
//
|
always @(pcreg or ex_branch_addrtarget or flag or branch_op or except_type
|
always @(pcreg or ex_branch_addrtarget or flag or branch_op or except_type
|
or except_start or operand_b or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
|
or except_start or operand_b or epcr or spr_pc_we or spr_dat_i or
|
|
except_prefix)
|
|
begin
|
casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
|
casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
|
{2'b00, `OR1200_BRANCHOP_NOP}: begin
|
{2'b00, `OR1200_BRANCHOP_NOP}: begin
|
pc = {pcreg + 30'd1, 2'b0};
|
pc = {pcreg + 30'd1, 2'b0};
|
ex_branch_taken = 1'b0;
|
ex_branch_taken = 1'b0;
|
end
|
end
|
{2'b00, `OR1200_BRANCHOP_J}: begin
|
{2'b00, `OR1200_BRANCHOP_J}: begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display("%t: BRANCHOP_J: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);
|
$display("%t: BRANCHOP_J: pc <= ex_branch_addrtarget %h"
|
|
, $time, ex_branch_addrtarget);
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
pc = {ex_branch_addrtarget, 2'b00};
|
pc = {ex_branch_addrtarget, 2'b00};
|
ex_branch_taken = 1'b1;
|
ex_branch_taken = 1'b1;
|
end
|
end
|
{2'b00, `OR1200_BRANCHOP_JR}: begin
|
{2'b00, `OR1200_BRANCHOP_JR}: begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display("%t: BRANCHOP_JR: pc <= operand_b %h", $time, operand_b);
|
$display("%t: BRANCHOP_JR: pc <= operand_b %h",
|
|
$time, operand_b);
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
pc = operand_b;
|
pc = operand_b;
|
ex_branch_taken = 1'b1;
|
ex_branch_taken = 1'b1;
|
end
|
end
|
{2'b00, `OR1200_BRANCHOP_BF}:
|
{2'b00, `OR1200_BRANCHOP_BF}:
|
if (flag) begin
|
if (flag) begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display("%t: BRANCHOP_BF: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);
|
$display("%t: BRANCHOP_BF: pc <= ex_branch_addrtarget %h",
|
|
$time, ex_branch_addrtarget);
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
pc = {ex_branch_addrtarget, 2'b00};
|
pc = {ex_branch_addrtarget, 2'b00};
|
ex_branch_taken = 1'b1;
|
ex_branch_taken = 1'b1;
|
end
|
end
|
| Line 262... |
Line 210... |
ex_branch_taken = 1'b0;
|
ex_branch_taken = 1'b0;
|
end
|
end
|
else begin
|
else begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display("%t: BRANCHOP_BNF: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);
|
$display("%t: BRANCHOP_BNF: pc <= ex_branch_addrtarget %h",
|
|
$time, ex_branch_addrtarget);
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
pc = {ex_branch_addrtarget, 2'b00};
|
pc = {ex_branch_addrtarget, 2'b00};
|
ex_branch_taken = 1'b1;
|
ex_branch_taken = 1'b1;
|
end
|
end
|
{2'b00, `OR1200_BRANCHOP_RFE}: begin
|
{2'b00, `OR1200_BRANCHOP_RFE}: begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
|
$display("%t: BRANCHOP_RFE: pc <= epcr %h",
|
|
$time, epcr);
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
pc = epcr;
|
pc = epcr;
|
ex_branch_taken = 1'b1;
|
ex_branch_taken = 1'b1;
|
end
|
end
|
| Line 283... |
Line 233... |
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display("Starting exception: %h.", except_type);
|
$display("Starting exception: %h.", except_type);
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V};
|
pc = {(except_prefix ?
|
|
`OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P),
|
|
except_type, `OR1200_EXCEPT_V};
|
ex_branch_taken = 1'b1;
|
ex_branch_taken = 1'b1;
|
end
|
end
|
default: begin
|
default: begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
| Line 304... |
Line 256... |
// PC register
|
// PC register
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
// default value
|
// default value
|
if (rst) begin
|
if (rst) begin
|
//pcreg_default <= #1 30'd63;
|
pcreg_default <= #1 `OR1200_BOOT_PCREG_DEFAULT; // jb
|
pcreg_default <= #1 /*30'd63 */ `OR1200_BOOT_PCREG_DEFAULT; // jb
|
|
pcreg_select <= #1 1'b1; // select async. value due to reset state
|
pcreg_select <= #1 1'b1; // select async. value due to reset state
|
end
|
end
|
// selected value (different from default) is written into FF after reset state
|
// selected value (different from default) is written into FF after
|
|
// reset state
|
else if (pcreg_select) begin
|
else if (pcreg_select) begin
|
pcreg_default <= #1 pcreg_boot[31:2]; // dynamic value can only be assigned to FF out of reset!
|
// dynamic value can only be assigned to FF out of reset!
|
|
pcreg_default <= #1 pcreg_boot[31:2];
|
pcreg_select <= #1 1'b0; // select FF value
|
pcreg_select <= #1 1'b0; // select FF value
|
end
|
end
|
else if (spr_pc_we) begin
|
else if (spr_pc_we) begin
|
pcreg_default <= #1 spr_dat_i[31:2];
|
pcreg_default <= #1 spr_dat_i[31:2];
|
end
|
end
|
else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch) begin
|
else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i
|
|
& !genpc_refetch) begin
|
pcreg_default <= #1 pc[31:2];
|
pcreg_default <= #1 pc[31:2];
|
end
|
end
|
|
|
// select async. value for pcreg after reset - PC jumps to the address selected after boot!
|
// select async. value for pcreg after reset - PC jumps to the address selected
|
//assign pcreg_boot = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1;
|
// after boot.
|
assign pcreg_boot = `OR1200_BOOT_ADR; // changed JB
|
assign pcreg_boot = `OR1200_BOOT_ADR; // changed JB
|
|
|
always @(pcreg_boot or pcreg_default or pcreg_select)
|
always @(pcreg_boot or pcreg_default or pcreg_select)
|
if (pcreg_select)
|
if (pcreg_select)
|
pcreg = pcreg_boot[31:2]; // async. value is selected due to reset state
|
// async. value is selected due to reset state
|
|
pcreg = pcreg_boot[31:2];
|
else
|
else
|
pcreg = pcreg_default ; // FF value is selected 2nd clock after reset state
|
// FF value is selected 2nd clock after reset state
|
|
pcreg = pcreg_default ;
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
